Renesas F-ZTAT H8 Series Hardware Manual page 321

SCI3 operates as follows during data transmission in synchronous mode.
SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data
written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).
Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is
requested.
If clock output is selected, SCI3 outputs eight serial clock pulses. If an external clock is used, data
is output in synchronization with the clock input.
Serial data is transmitted from pin TXD in order from LSB (bit 0) to MSB (bit 7).
Then TDRE is checked as the MSB (bit 7) is being transmitted. If TDRE is 0, data is transferred
from TDR to TSR, and after the MSB (bit 7) is sent, transmission of the next frame starts. If
TDRE is 1, the TEND bit in SSR is set to 1, and after the MSB (bit 7) has been sent, the MSB
state is maintained. A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1.
After data transmission ends, pin SCK
Note: Data transmission cannot take place while any of the receive error flags (OER, FER, PER)
is set to 1. Be sure to confirm that these error flags are cleared to 0 before starting
transmission.
Figure 10.16 shows a typical SCI3 transmit operation in synchronous mode.
Serial
clock
Serial data
TDRE
TEND
LSI TXI
request
operation
User
processing
Figure 10.16 Typical SCI3 Transmit Operation in Synchronous Mode
is held at the high level.
3
Bit 0 Bit 1
1 frame
TDRE cleared to 0
Write data in TDR
10. Serial Communication Interface
Bit 7 Bit 0 Bit 1
TXI
request
Rev.3.00 Jul. 19, 2007 page 295 of 532
Bit 6 Bit 7
1 frame
TEI request
REJ09B0397-0300