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Bits 2 to 0—Clock Select L (CKSL2 to CKSL0): Bits 2 to 0 select the input to TCFL from four
internal clock signals or external event input.
Bit 2: CKSL2
Bit 1: CKSL1
0
*
1
0
1
Legend: * Don't care
Note:
1. The edge of the external event signal is selected by bit IEG3 in the IRQ edge select
register (IEGR). See section 3.3.2, Interrupt Control Registers for details on the IRQ
edge select register. Note that switching the TMIF pin function by changing bit IRQ3 in
port mode register 1 (PMR1) from 0 to 1 or from 1 to 0 while the TMIF pin is at the low
level may cause the timer F counter to be incremented.
Timer Control/Status Register F (TCSRF)
Bit
OVFH
Initial value
Read/Write
R/W*
Note:
Only 0 can be written to clear flag.
*
TCSRF is an 8-bit read/write register. It is used for counter clear selection, overflow and compare
match indication, and enabling of interrupts caused by timer overflow.
Upon reset, TCSRF is initialized to H'00.
Bit 7—Timer overflow flag H (OVFH): Bit 7 is a status flag indicating TCFH overflow (H'FF to
H'00). This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 7: OVFH
Description
0
Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting condition:
Set when the value of TCFH goes from H'FF to H'00
Bit 0: CKSL0
*
0
1
0
1
7
6
5
CMFH
OVIEH
0
0
0
R/W*
R/W
Description
External event (TMIF). Rising or falling edge is
1
counted*
Internal clock: φ/32
Internal clock: φ/16
Internal clock: φ/4
Internal clock: φ/2
4
3
CCLRH
OVFL
0
0
R/W
R/W*
Rev.3.00 Jul. 19, 2007 page 233 of 532
9. Timers
(initial value)
2
1
CMFL
OVIEL
CCLRL
0
0
R/W*
R/W
(initial value)
REJ09B0397-0300
0
0
R/W
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