Renesas F-ZTAT H8 Series Hardware Manual page 295

value of 1 is received, the receive data full interrupt (RXI) and receive error interrupt
(ERI) are disabled and serial status register (SSR) flags RDRF, FER, and OER are not
set. When the multiprocessor bit receives a 1, the MPBR bit of SSR is set to 1, MPIE is
automatically cleared to 0, RXI and ERI interrupts are enabled (provided bits TIE and
RIE in SCR3 are set to 1), and setting of the RDRF, FER, and OER flags is enabled.
Bit 2—Transmit End Interrupt Enable (TEIE): Bit 2 enables or disables the transmit end
interrupt (TEI) requested if there is no valid transmit data in TDR when the MSB is transmitted.
Bit 2: TEIE Description
0 Transmit end interrupt (TEI) disabled
1 Transmit end interrupt (TEI) enabled*
Note: * A TEI interrupt can be cleared by clearing the SSR bit TDRE to 0 and clearing the
transmit end bit (TEND) to 0, or by clearing bit TEIE to 0.
Bits 1 and 0—Clock Enable 1, 0 (CKE1, CKE0): Bits 1 and 0 select the clock source and enable
or disable clock output at pin SCK
pin SCK is a general I/O port, a clock output pin, or a clock input pin.
3
Note that the CKE0 setting is valid only when operation is in asynchronous mode using an internal
clock (CKE1 = 0). This bit is invalid in synchronous mode or when using an external clock
(CKE1 = 1). In synchronous mode and in external clock mode, clear CKE0 to 0. After setting bits
CKE1 and CKE0, the operation mode must first be set in the serial mode register (SMR).
See table 10.12 in section 10.3.3, Operation, for details on clock source selection.
Bit 1: CKE1 Bit 0: CKE0
0 0
0 1
1 0
1 1
Notes: 1. Initial value
2. A clock is output with the same frequency as the bit rate.
3. Input a clock with a frequency 16 times the bit rate.
. The combination of bits CKE1 and CKE0 determines whether
3
Communication Mode
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
10. Serial Communication Interface
Clock Source SCK
Internal clock I/O port
Internal clock Serial clock output
Internal clock Clock output
Reserved Reserved
External clock Clock input
External clock Serial clock input
Reserved Reserved
Reserved Reserved
Rev.3.00 Jul. 19, 2007 page 269 of 532
(initial value)
Pin Function
3
1
*
1
*
2
*
3
*
REJ09B0397-0300