Renesas F-ZTAT H8 Series Hardware Manual page 294

10. Serial Communication Interface
Bit 5—Transmit Enable (TE): Bit 5 enables or disables the start of a transmit operation.
Bit 5: TE Description
0 Transmit operation disabled
1 Transmit operation enabled
Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SSR) is fixed
at 1.
2. In this state, writing transmit data in TDR clears bit TDRE in SSR to 0 and starts serial
data transmission.
Before setting TE to 1 it is necessary to set the transmit format in SMR. When
performing simultaneous transmission and reception in synchronous mode, TE and RE
should be set to 1 simultaneously by a single instruction when they are both cleared to
0.
Bit 4—Receive Enable (RE): Bit 4 enables or disables the start of a receive operation.
Bit 4: RE Description
0 Receive operation disabled
1 Receive operation enabled
Notes: 1. When RE is cleared to 0, this has no effect on the SSR flags RDRF, FER, PER, and
OER, which retain their states.
2. Serial data receiving begins when, in this state, a start bit is detected in asynchronous
mode, or serial clock input is detected in synchronous mode.
Before setting RE to 1 it is necessary to set the receive format in SMR. When
performing simultaneous transmission and reception in synchronous mode, TE and RE
should be set to 1 simultaneously by a single instruction when they are both cleared to
0.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Bit 3 enables or disables multiprocessor
interrupt requests. This setting is valid only in asynchronous mode, and only when the
multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1. This bit is ignored
when COM is set to 1 or when bit MP is cleared to 0.
Bit 3: MPIE Description
0 Multiprocessor interrupt request disabled (ordinary receive operation)
Clearing condition:
Multiprocessor bit receives a data value of 1
1 Multiprocessor interrupt request enabled*
Note: * SCI3 does not transfer receive data from RSR to RDR, does not detect receive errors,
and does not set status flags RDRF, FER, and OER in SSR. Until a multiprocessor bit
Rev.3.00 Jul. 19, 2007 page 268 of 532
REJ09B0397-0300
1
(TXD is a general I/O port)
*
2
(TXD is the transmit data pin)
*
1
(RXD is a general I/O port)
*
2
(RXD is the receive data pin)
*
(initial value)
(initial value)
(initial value)