Renesas F-ZTAT H8 Series Hardware Manual page 63

Table 2.2 Effective Address Calculation
Addressing Mode and
No. Instruction Format
1
Register direct, Rn
15 8 7
op
2
Register indirect, @Rn
15 7 6
op
3 Register indirect with
displacement, @(d:16, Rn)
15 7 6
op
disp
4 Register indirect with
post-increment, @Rn+
15 7 6
op
Register indirect with
pre-decrement, @–Rn
15 7 6
op
Effective Address
Calculation Method
4 3 0
rm rn
15
Contents (16 bits) of
register indicated by rm
4 3 0
rm
15
Contents (16 bits) of
register indicated by rm
4 3 0
rm
15
Contents (16 bits) of
register indicated by rm
4 3 0
rm
15
register indicated by rm
4 3 0
Incremented or
rm
decremented by 1 if
operand is byte size,
and by 2 if word size
0
0
disp
0
1 or 2
0
Contents (16 bits) of
1 or 2
Rev.3.00 Jul. 19, 2007 page 37 of 532
2. CPU
Effective Address (EA)
3 0 3 0
rm rn
Operand is contents of
registers indicated by rm/rn
15
15
15
15
REJ09B0397-0300
0
0
0
0