Renesas F-ZTAT H8 Series Hardware Manual page 471

Mnemonic
DIVXU.B Rs, Rd
AND.B #xx:8, Rd
AND.B Rs, Rd
OR.B #xx:8, Rd
OR.B Rs, Rd
XOR.B #xx:8, Rd
XOR.B Rs, Rd
NOT.B Rd
SHAL.B Rd
SHAR.B Rd
SHLL.B Rd
SHLR.B Rd
ROTXL.B Rd
ROTXR.B Rd
ROTL.B Rd
ROTR.B Rd
Operation
B Rd16÷Rs8 → Rd16 (RdH:
remainder, RdL: quotient)
B Rd8∧#xx:8 → Rd8
B Rd8∧Rs8 → Rd8
B Rd8∨#xx:8 → Rd8
B Rd8∨Rs8 → Rd8
B Rd8⊕#xx:8 → Rd8
B Rd8⊕Rs8 → Rd8
B Rd → Rd
B
C
b b
7
B
b b
7 0
B
C
b b
7
B
0
b b
7 0
B
C
b
7
B
b b
7 0
B
C
b b
7
B
b b
7 0
Appendix A CPU Instruction Set
Addressing Mode/
Instruction Length (Bytes)
2
2
2
2
2
2
2
2
2
0
0
2
C
2
0
0
2
C
2
b
0
2
C
2
0
2
C
Rev.3.00 Jul. 19, 2007 page 445 of 532
Condition Code
I H N Z V C
⎯ ⎯ (5) (6) ⎯ ⎯ 14
⎯ ⎯ 0 ⎯ 2
⎯ ⎯ 0 ⎯ 2
⎯ ⎯ 0 ⎯ 2
⎯ ⎯ 0 ⎯ 2
⎯ ⎯ 0 ⎯ 2
⎯ ⎯ 0 ⎯ 2
⎯ ⎯ 0 ⎯ 2
⎯ ⎯
2
⎯ ⎯
0 2
⎯ ⎯
0 2
⎯ ⎯ 0
0 2
⎯ ⎯
0 2
⎯ ⎯
0 2
⎯ ⎯
0 2
⎯ ⎯
0 2
REJ09B0397-0300