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IRR1—Interrupt request register 1
Bit
7
IRRTA
Initial value
0
Read/Write
R/W
IRQ to IRQ interrupt request flag
4
0 [Clearing conditions]
When IRRI4 = 1, it is cleared by writing 0
When 0 is written to IRRI4 when IRRI4 = 1
The same also applies to IRRI3—IRRI0
1 [Setting conditions]
When pin IRQ is set to interrupt input and the designated signal edge is
detected
When pin IRQ
The same also applies to IRRI3—IRRI0
SCI1 interrupt request flag
0 [Clearing condition]
When IRRS1 = 1, it is cleared by writing 0
1 [Setting condition]
When an SCI1 transfer is completed
Timer A interrupt request flag
0 [Clearing condition]
When IRRTA = 1, it is cleared by writing 0
1 [Setting condition]
When the timer A counter overflows from H'FF to H'00
Notes: 1. IRRS1 and IRRI2 are functions of the H8/3857 Group only.
In the H8/3854 Group these bits are reserved, and are always 0.
2. Only a write of 0 for flag clearing is possible.
6
5
⎯
*1
IRRS1
0
1
⎯
*2
*2
R/W
0
4
is set to interrupt input and the designated edge is input at this pin
4
Appendix B Internal I/O Registers
H'F6
4
3
IRRI4
IRRI3
IRRI2
0
0
*2
*2
R/W
R/W
R/W
Rev.3.00 Jul. 19, 2007 page 505 of 532
System control
2
1
0
*1
IRRI1
IRRI0
0
0
0
*2
*2
R/W
R/W
REJ09B0397-0300
*2
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