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6. ROM
RAM
Programming data
storage area
(32 bytes)
Reprogramming
data storage area
(32 bytes)
Notes:
1.
2.
3.
4.
5.
6.
Programming Data
Note: The memory erased state is "1". Programming is performed on "0" reprogramming data.
Rev.3.00 Jul. 19, 2007 page 142 of 532
REJ09B0397-0300
Set SWE bit in FLMCR1
Store 32-byte programming data in programming
data area and reprogramming data area
Consecutively write 32-byte data in repro-
gramming data area in RAM to flash memory
Set PSU bit in FLMCR2
Clear PSU bit in FLMCR2
H'FF dummy write to verify address
Increment address
Reprogramming data computation
Transfer reprogramming data to reprogramming data area
No
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
Programming should be performed in the erased state. Do not perform additional programming on addresses that have
already been programmed. (Perform 32-byte programming on memory after all 32 bytes have been erased.)
Data transfer is performed by byte transfer (word transfer is not possible). The lower 8 bits of the first address written
to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer must be performed even if writing
fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses.
Verify data is read in 16-bit (word) units.
Reprogramming data is determined by the operation shown in the table below (comparison between the data stored
in the programming data area and the verify data). Bits for which the reprogramming data is 0 are programmed in the
next programming loop. Therefore, even bits for which programming has been completed will be subjected to programming
once again if the result of the subsequent verify operation is No.
A 32-byte area for storing programming data and a 32-byte area for storing reprogramming data must be provided
in RAM. The contents of the latter are rewritten in accordance with reprogramming data computation.
The values of x, y, z, α, β, γ, ε, η, and N are shown in section 15.2.6, Flash Memory Characteristics.
Verify Data
Reprogramming Data
0
0
0
1
1
0
1
1
Figure 6.12 Program/Program-Verify Flowchart
START
1
*
Wait (x) μs
6
*
5
*
n = 1
m = 0
2
*
Enable WDT
Wait (y) μs
6
*
Set P bit in FLMCR1
Start of programming
Wait (z) μs
6
*
Clear P bit in FLMCR1
End of programming
Wait (α) μs
6
*
Wait (β) μs
6
*
Disable WDT
Set PV bit in FLMCR1
Wait (γ) μs
6
*
Wait (ε) μs
6
*
3
*
Read verify data
No
Programming data =
verify data?
m = 1
Yes
4
*
*
32-byte
data verification
completed?
Yes
Wait (η) μs
6
*
No
m = 0?
Yes
Clear SWE bit in FLMCR1
End of programming
Comments
Programmed bits are not reprogrammed
1
Programming incomplete; reprogram
0
⎯
1
Still in erased state; no action
1
n ← n + 1
5
*
6
No
n ≥ N?
Yes
Programming failure
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