Renesas F-ZTAT H8 Series Hardware Manual page 132

8-bit single-chip microcomputer
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5. Power-Down Modes
Bit 4—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency
at which the watch clock signal (φ
relation to the oscillator clock (φ
to 10 MHz, clear NESEL to 0.
Bit 4: NESEL
Description
Sampling rate is φ
0
Sampling rate is φ
1
Bit 3—Direct Transfer on Flag (DTON): This bit designates whether or not to make direct
transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP
instruction is executed. The mode to which the transition is made after the SLEEP instruction is
executed depends on a combination of this and other control bits.
Bit 3: DTON
Description
0
When a SLEEP instruction is executed in active mode, a transition is made to
standby mode, watch mode, or sleep mode.
When a SLEEP instruction is executed in subactive mode, a transition is made
to watch mode or subsleep mode.
1
When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1.
When a SLEEP instruction is executed in active (medium-speed) mode, a
direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0,
and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1.
When a SLEEP instruction is executed in subactive mode, a direct transition is
made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and
MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON =
0, and MSON = 1.
Bit 2—Medium Speed on Flag (MSON): After standby, watch, or sleep mode is cleared, this bit
selects active (high-speed) or active (medium-speed) mode.
Bit 2: MSON
Description
0
Operation is in active (high-speed) mode
1
Operation is in active (medium-speed) mode
Rev.3.00 Jul. 19, 2007 page 106 of 532
REJ09B0397-0300
) generated by the subclock pulse generator is sampled, in
W
) generated by the system clock pulse generator. When φ
OSC
/16
OSC
/4
OSC
= 2
OSC
(initial value)
(initial value)
(initial value)

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