Renesas F-ZTAT H8 Series Hardware Manual page 72

2. CPU
Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
15
op
15
15
op
15
op
15
op
15
op
15
Legend:
op: Operation field
rm, rn: Register field
IMM: Immediate data
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes
Rev.3.00 Jul. 19, 2007 page 46 of 532
REJ09B0397-0300
8 7
rm
8 7
op
8 7
rm
8 7
rn
8 7
rm
8 7
rn
8 7
op
0
ADD, SUB, CMP,
rn
ADDX, SUBX (Rm)
0
ADDS, SUBS, INC, DEC,
rn
DAA, DAS, NEG, NOT
0
rn
MULXU, DIVXU
0
ADD, ADDX, SUBX,
IMM
CMP (#XX:8)
0
rn
AND, OR, XOR (Rm)
0
IMM
AND, OR, XOR (#xx:8)
0
SHAL, SHAR, SHLL, SHLR,
rn
ROTL, ROTR, ROTXL, ROTXR