Renesas F-ZTAT H8 Series Hardware Manual page 287

8-bit single-chip microcomputer
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• There are six interrupt sources: transmit end, transmit data empty, receive data full, overrun
error, framing error, and parity error.
Block Diagram
Figure 10.3 shows a block diagram of SCI3.
External
clock
SCK
3
Clock
TXD
RXD
Legend:
RSR:
Receive shift register
RDR:
Receive data register
TSR:
Transmit shift register
TDR:
Transmit data register
SMR:
Serial mode register
SCR3:
Serial control register 3
SSR:
Serial status register
BRR:
Bit rate register
BRC:
Bit rate counter
Baud rate
generator
BRC
Transmit/receive
control
TSR
RSR
Figure 10.3 SCI3 Block Diagram
10. Serial Communication Interface
Internal clock
(φ/64, φ/16, φ/4, φ)
BRR
SMR
SCR3
SSR
TDR
RDR
Rev.3.00 Jul. 19, 2007 page 261 of 532
Interrupt
requests
(TEI, TXI,
RXI, ERI)
REJ09B0397-0300

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