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Appendix B Internal I/O Registers
SYSCR1—System control register 1
Bit
SSBY
Initial value
Read/Write
R/W
Software standby
Legend:
Don't care
*
Rev.3.00 Jul. 19, 2007 page 500 of 532
REJ09B0397-0300
7
6
5
STS2
STS1
0
0
0
R/W
R/W
Standby timer select 2 to 0
0
1 *
0 When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode.
When a SLEEP instruction is executed in subactive mode, a transition is
made to subsleep mode.
1
When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode.
When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode.
H'F0
4
3
STS0
LSON
0
0
R/W
R/W
Low speed on flag
0 The CPU operates on the system clock (φ)
1 The CPU operates on the subclock (φ
0 0
Wait time = 8,192 states
1
Wait time = 16,384 states
1 0
Wait time = 32,768 states
1
Wait time = 65,536 states
Wait time = 131,072 states
*
System control
2
1
0
⎯
⎯
⎯
1
1
1
⎯
⎯
⎯
SUB
)
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