Renesas F-ZTAT H8 Series Hardware Manual page 211

Bits 7 and 6—Reserved Bits: Bits 7 and 6 are reserved; they are always read as 1, and cannot be
modified.
Bits 5 and 4—Reserved Bits: Bits 5 and 4 are reserved; they should always be cleared to 0.
Bit 3—P4 /IRQ Pin Function Switch (IRQ0): This bit selects whether pin P4
3 0
or as IRQ
P4 .
3 0
Bit 3: IRQ0 Description
0 Functions as P4
Functions as IRQ
1
Note: Rising or falling edge sensing can be selected for the IRQ
Bit 2—P3 /SO Pin PMOS Control (POF1): This bit controls the on/off state of the PMOS
2 1
transistor in the P3 /SO
2
Bit 2: POF1 Description
0 CMOS output
1 NMOS open-drain output
In the H8/3854 Group, bit 2 is reserved, and must always be cleared to 0.
Bit 1—P2 /UD Pin Function Switch (UD): This bit selects whether pin P2
1
as UD.
Bit 1: UD Description
0 Functions as P2
1 Functions as UD input pin
In the H8/3854 Group, bit 1 is reserved, and must always be cleared to 0.
Bit 0: P2 /IRQ /ADTRG Pin Function Switch (IRQ4): This bit selects whether pin
0 4
P2 /IRQ /ADTRG is used as P2
0 4
Bit 0: IRQ4 Description
0 Functions as P2
Functions as IRQ
1
Note: Rising or falling edge sensing can be selected for the IRQ
See section 12.3.2, Start of A/D Conversion by External Trigger Input, for the ADTRG pin
setting.
input pin
3
input pin
0
pin output buffer.
1
I/O pin
1
or as IRQ
/ADTRG.
0 4
I/O pin
0
/ADTRG input pin
4
3
pin.
0
/UD is used as P2
1
pin.
4
Rev.3.00 Jul. 19, 2007 page 185 of 532
8. I/O Ports
/IRQ is used as
0
(initial value)
(initial value)
or
1
(initial value)
(initial value)
REJ09B0397-0300