Renesas F-ZTAT H8 Series Hardware Manual page 104

3. Exception Handling
Interrupt Enable Register 2 (IENR2)
Bit
IENDT
Initial value
Read/Write R/W
Note: * Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to
0.
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer
interrupt requests.
Bit 7: IENDT Description
0 Disables direct transfer interrupt requests
1 Enables direct transfer interrupt requests
Bit 6—A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter
interrupt requests.
Bit 6: IENAD Description
0 Disables A/D converter interrupt requests
1 Enables A/D converter interrupt requests
Bits 5 and 4—Reserved Bits: Bits 5 and 4 are reserved; they should always be cleared to 0.
Bit 3—Timer FH Interrupt Enable (IENTFH): Bit 3 enables or disables timer FH compare
match and overflow interrupt requests.
Bit 3: IENTFH Description
0 Disables timer FH interrupts
1 Enables timer FH interrupts
Rev.3.00 Jul. 19, 2007 page 78 of 532
REJ09B0397-0300
7 6 5
⎯
IENAD
0 0 0
R/W R/W
4 3
⎯
IENTFH IENTFL
0 0
R/W R/W R/W
2 1 0
IENTC* IENTB
0 0 0
R/W R/W
(initial value)
(initial value)
(initial value)