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Interrupt Request Register 2 (IRR2)
Bit
IRRDT
Initial value
Read/Write
R/W*
Notes: 1. Only a write of 0 for flag clearing is possible.
2. Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to
0.
IRR2 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a direct
transfer, A/D converter, timer FH, timer FL, timer C, or timer B interrupt is requested. The flags
are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each
flag.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7: IRRDT
Description
0
Clearing condition:
When IRRDT = 1, it is cleared by writing 0
1
Setting condition:
When DTON = 1 and a direct transfer is made immediately after a SLEEP
instruction is executed
Bit 6—A/D Converter Interrupt Request Flag (IRRAD)
Bit 6: IRRAD
Description
0
Clearing condition:
When IRRAD = 1, it is cleared by writing 0
1
Setting condition:
When A/D conversion is completed and ADSF is reset
Bits 5 and 4—Reserved Bits: Bits 5 and 4 are reserved; they should always be cleared to 0.
7
6
5
⎯
IRRAD
0
0
0
⎯
1
1
R/W*
4
3
2
⎯
IRRTFH IRRTFL IRRTC*
0
0
0
⎯
1
R/W*
R/W*
Rev.3.00 Jul. 19, 2007 page 81 of 532
3. Exception Handling
1
0
2
IRRTB
0
0
1
1
1
R/W*
R/W*
(initial value)
(initial value)
REJ09B0397-0300
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