Data Register (Idar) - Fujitsu F2MC-16LX Hardware Manual

22.2.5 Data Register (IDAR)

This section describes the configuration and functions of the data register (IDAR).
I Data register (IDAR)
The diagram below shows the bit configuration of the data register (IDAR).
Data register
Address: 00008C
[Bit 7] D7 to D0
These bits are used as data bits.
These bits constitute a data register for serial transfer starting with the MSB. If data is
received (TRX = 0), the data output value becomes "1".
With respect to writing, this register consists of a double buffer. If the bus is active (BB = 1),
write data is loaded separately for each byte transfer operation into the register for serial
transfer. When the register is directly read for serial transfer, note that the receive data is
only valid if the INT bit is set.
7 6
H
D7 D6
Read/write
(R/W)(R/W)(R/W) (R/W)(R/W)(R/W)(R/W)(R/W)
Initial value
(X) (X)
5 4 3 2 1
D5 D4 D3 D2 D1
(X) (X) (X) (X) (X)
2
CHAPTER 22 I C INTERFACE
0 Bit number
D0 IDAR
(X)
435