Address Register (Iadr)/Data Register (Idar) - Fujitsu MB91150 Series Hardware Manual

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CHAPTER 16 I C INTERFACE

16.3.3 Address Register (IADR)/Data Register (IDAR)

The address register (IADR) is used to specify a slave address.
The data register (IADR) is used to perform serial transfer.
I Address register (IADR)
The address register (IADR) has the following bit configuration:
Address
Bit15
−
0000_0122
H
−
R/W: Can be read and written
[bits 14 to 8] slave address (A6 to A0)
This register specifies a slave address. After address data is received in slave mode, it is
compared with that of the DAR register. If both values match, Acknowledge is transmitted to
the master.
I Data register (IDAR)
The data register (IDAR) has the following bit configuration:
Address
Bit7
0000_0125
D7
H
R/W
R/W: Can be read and written :
[bit 7 to 0] data bit (D7 to D0)
This data register is used to perform serial transfer, during which data is transferred starting
from the MSB. At the time of data reception (TRX=1), the output data value becomes 1.
This register has a double buffer on the writing side. When the bus is in use (BB=1), data to
be written is loaded into the serial transfer register at each byte transfer. Because the data of
the serial transfer register is directly read during data reading, received data is valid only
when the INT bit is set.
356
Bit14 Bit13 Bit12 Bit11
A6 A5 A4
R/W R/W R/W R/W
Bit6 Bit5 Bit4 Bit3
D6 D5 D4
R/W R/W R/W R/W
Bit10 Bit9 Bit8
A3 A2 A1 A0
R/W R/W R/W
Bit2 Bit1 Bit0
D3 D2 D1 D0
R/W R/W R/W
Initial value -XXXXXXX
B
Initial value XXXXXXXX
B