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MB90335 Series
13.2.3
PWC Ratio of Dividing Frequency Control Register (DIVR)
Configuration and function of PWC Ratio of dividing frequency control register (DIVR)
are described.
■ PWC Ratio of Dividing Frequency Control Register (DIVR)
Figure 13.2-4 shows the bit configuration of a PWC ratio of dividing frequency control register (DIVR).
Figure 13.2-4 Bit Configuration of PWC Ratio of Dividing Frequency Control Register (DIVR)
bit
7
−
000060
H
−
(
)
(
R/W : Readable/Writable
−
: Undefined
[bit7 to bit2] Undefined bits
The reading value is irregular. No effect on writing.
[bit1, bit0] DIV1, DIV0 (division ratio selection)
This register is used in the division cycle measurement mode (PWCSR bit2, bit1, bit0: MOD2, MOD1,
MOD0 = 001
In the division cycle measurement mode, pulses input to the measurement pin are divided by the
division ratio set in the DIVR register and a single cycle width is measured after dividing.
Table 13.2-7 Division Ratio Selection
DIV1
0
0
1
1
• Initialized to "00
• Reading and writing are allowed.
Note:
Rewriting after the startup is an interdiction. Always perform the write operation before start or after
stop.
CM44-10137-6E
6
5
4
3
−
−
−
−
−
−
−
−
)
(
)
(
)
(
)
) and has no meaning in the other mode else.
B
DIV0
0
1
0
1
" at reset.
B
FUJITSU MICROELECTRONICS LIMITED
2
1
0
DIVR
−
DIV1
DIV0
PWC ratio of dividing frequency control register
−
Initial value ------00
(
)
(R/W) (R/W)
Count clock selection
4-dividing frequency [Initial value]
16-frequency division
64-frequency division
256-frequency division
CHAPTER 13 PWC TIMER
13.2 Register of PWC Timer
B
299
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