Divide Ratio Control Register (Divr) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

18.3 Regiaters and Register Details

18.3.3 Divide Ratio Control Register (DIVR)

Divide Ratio Control Register
Address : 000058
Read/write
Initial value
This register is only used in divided period count mode (bits 2, 1, 0: MOD2, 1, 0 of PWCSR = "011").
In divided period count mode, pulses input from the count pin are divided by the divide ratio set in
this register and the period of the divided signal is measured. The divide ratio is selected as follows.
DIV1
0
0
1
1
After a reset: Initialized to "00
Readable and writable.
Note: Changing the setting after activating the timer is prohibited. Only write to these bits before
starting or after halting the timer.
250 Chapter 18: Pulse Width Counter (PWC) Timer
7 6
—
—
H
(-) (-)
(-) (-)
DIV0
0
1
0
1
".
B
5 4 3
— — —
(-) (-) (-)
(-) (-) (-)
Divide Ratio Selection
2
2 = divide by
4
2 = divide by 16
6
2 = divide by 64
8
= divide by 256
2
2 1 0
— DIV1 DIV0 DIVR
(-) (R/W) (R/W)
(-) (0) (0)
4 (Initial value)
MB90580 Series
Bit number