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are driven to logic high. A23–A20 are only available in address mode (AMODE=0). A15–
A1 are multiplexed with DRAM address.
2.1.2 Address Strobe (
Assertion of this three-state signal indicates that the information on the address bus is a
valid address.
2.1.3 Bus Error (
Assertion of this bi-directional, open-drain signal indicates a problem in the current bus
cycle. The MC68306 can assert this signal to terminate a bus cycle when no external
response is received. An external source can assert BERR to indicate a problem such as:
1. No response from a device
2. No interrupt vector number returned
3. An illegal access request rejected by a memory management unit
4. Some other application-dependent error
Either the processor retries the bus cycle or performs exception processing, as
determined by interaction between the bus error signal and the halt signal.
2.1.4 Bus Request (
This input can be wire-ORed with bus request signals from all other devices that could be
bus masters. Assertion of this signal indicates to the processor that some other device
needs to become the bus master. Bus requests can be issued at any time during a bus
cycle or between cycles.
2.1.5 Bus Grant (
This output signal indicates to all other potential bus master devices that the processor will
relinquish bus control at the end of the current bus cycle.
2.1.6 Bus Grant Acknowledge (
Assertion of this input indicates that some other device has become the bus master. This
signal should not be asserted until the following conditions are met:
1. A bus grant has been received.
2. Address strobe is inactive, which indicates that the microprocessor is not using the
bus.
3. Data transfer acknowledge is inactive, which indicates that neither memory nor
peripherals are using the bus.
4. Bus grant acknowledge is inactive, which indicates that no other device is claiming
bus mastership.
2-6
AS
)
BERR
)
BR
)
BG
)
BGACK
MC68306 USER'S MANUAL
)
MOTOROLA
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