Bus Request (Mc68020); Bus Grant (Mc68020); Bus Grant Acknowledge (Mc68020) - Motorola MC68020 User Manual

5.7.1.1 BUS REQUEST (MC68020). External devices capable of becoming bus masters
request the bus by asserting BR. BR can be a wire-ORed signal (although it need not be
constructed from open-collector devices) that indicates to the processor that some
external device requires control of the bus. The processor is at a lower bus priority level
than the external device and relinquishes the bus after it has completed the current bus
cycle (if one has started).
If no BGACK is received while BR is asserted, the processor remains bus master once BR
is negated. This prevents unnecessary interference with ordinary processing if the
arbitration circuitry inadvertently responds to noise or if an external device determines that
it no longer requires use of the bus before it has been granted mastership.
5.7.1.2 BUS GRANT (MC68020). The processor asserts BG as soon as possible after
receipt of the bus request. BG assertion immediately follows internal synchronization
except during a read-modify-write cycle or follows an internal decision to execute a bus
cycle. During a read-modify-write cycle, the processor does not assert BG until the entire
operation has completed. RMC is asserted to indicate that the bus is locked. In the case of
an internal decision to execute another bus cycle, BG is deferred until the bus cycle has
begun.
BG may be routed through a daisy-chained network or through a specific priority-encoded
network. The processor allows any type of external arbitration that follows the protocol.
5.7.1.3 BUS GRANT ACKNOWLEDGE (MC68020). Upon receiving BG, the requesting
device waits until AS, DSACK1/DSACK0, and BGACK are negated before asserting its
own BGACK. The negation of AS indicates that the previous master releases the bus after
specification #7 (refer to Section 10 Electrical Characteristics). The negation of
DSACK1/DSACK0 indicates that the previous slave has completed its cycle with the
previous master. Note that in some applications, DSACK1/DSACK0 might not be used in
this way.
General-purpose devices are connected to be dependent only on AS. When BGACK is
asserted, the device is the bus master until it negates BGACK. BGACK should not be
negated until all bus cycles required by the alternate bus master have been completed.
Bus mastership terminates at the negation of BGACK. The BR from the granted device
should be negated after BGACK is asserted. If another BR is still pending after the
assertion of BGACK, another BG is asserted within a few clocks of the negation of the the
first BG, as described in 5.7.1.4 Bus Arbitration Control (MC68020). Note that the
processor does not perform any external bus cycles before it reasserts BG in this case.
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