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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2
Error Handling
2-28
The CONFIG_ADDRESS and CONFIG_DATA registers are actually
represented in PCI space to the processor and are subject to the endian
functions. For example, the powerup location of the CONFIG_ADDRESS
register with respect to the MPC bus is $80000cf8 when Raven is in big-
endian mode. When Raven is switched to little-endian mode, the
CONFIG_ADDRESS register with respect to the MPC bus is $80000cfc.
Note that in both cases the address generated internal to the processor will
be $80000cf8.
The contents of the CONFIG_ADDRESS register are not subject to the
endian function.
The data associated with PIACK accesses is subject to the endian
swapping function. The address of a PIACK cycle is undefined, therefore
address modification during little-endian mode is not an issue.
The Raven will be capable of detecting and reporting the following errors
to one or more MPC masters:
MPC address bus time-out
J
PCI master signalled master abort
J
PCI master received target abort
J
PCI parity error
J
PCI system error
J
Each of these error conditions will cause an error status bit to be set in the
MPC Error Status Register. If a second error is detected while any of the
error bits is set, the OVFL bit is asserted, but none of the error bits are
changed. Each bit in the MPC Error Status Register may be cleared by
writing a 1 to it; writing a 0 to it has no effect. New error bits may be set
only when all previous error bits have been cleared.
When any bit in the MPC Error Status register is set, the Raven will
attempt to latch as much information as possible about the error in the
MPC Error Address and Attribute Registers. Information is saved as
follows:
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