Data Transfer Mechanism - Motorola MC68030 User Manual

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For synchronous bus cycles, external devices assert the synchronous ter-
mination signal (STERM) as part of the bus protocol. During a read cycle,
the assertion of STERM causes the processor to latch the data. During a write
cycle, it indicates that the external device has successfully stored the data.
In either case, it terminates the cycle and indicates that the transfer was made
to a 32-bit port. Refer to 7.3.2 Asynchronous Write Cycle for timing relation-
ships of STERM.
The bus error (BERR) signal is also a bus cycle termination indicator and can
be used in the absence of DSACKx or STERM to indicate a bus error condition.
It can also be asserted in conjunction with DSACKx or STERM to indicate a
bus error condition, provided it meets the appropriate timing described in
this section and in MC68030EC/D, MC68030 Electrical Specifications. Addi-
tionally, the BERR and HALT signals can be asserted together to indicate a
retry termination. Again, the BERR and HALT signals can be asserted simul-
taneously in lieu of or in conjunction with the DSACKx or STERM signals.
Finally, the autovector (AVEC) signal can be used to terminate interrupt ac-
knowledge cycles, indicating that the MC68030 should internally generate a
vector number to locate an interrupt handler routine. AVEC is ignored during
all other bus cycles.
7.2
DATA TRANSFER MECHANISM
The MC68030 architecture supports byte, word, and long-word operands
allowing access to 8-, 16-, and 32-bit data ports through the use of asyn-
chronous cycles controlled by DSACKO and DSACK1. It also supports syn-
chronous bus cycles to and from 32-bit ports, terminated by STERM. Byte,
word, and long-word operands can be located on any byte boundary, but
misaligned transfers may require additional bus cycles, regardless of port
size.
When the processor requests a burst mode fill operation, it asserts the cache
burst request (CBREQ) signal to attempt to fill four entries within a line in
one of the on-chip caches. This mode is compatible with nibble, static column,
or page mode dynamic RAMs. The burst fill operation uses synchronous bus
cycles, each terminated by STERM, to fetch as many as four long words.
7.2.1
Dynamic Bus Sizing
7-6
The MC68030 dynamically interprets the port size of the addressed device
during each bus cycle, allowing operand transfers to or from 8-, 16-, and 32-
bit ports. During an asynchronous operand transfer cycle, the slave device
MC68030 USER'S MANUAL
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