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Timing Comments Assertion-Must occur when the MPC750 must be prevented from
using the data bus.
Negation-May occur whenever the data bus is available.
7.2.7 Data Transfer Signals
Like the address transfer signals, the data transfer signals are used to transmit data and to
generate and monitor parity for the data transfer. For a detailed description of how the data
transfer signals interact, see Section 8.4.3, "Data Transfer."
7.2.7.1 Data Bus (DH[O-31], DL[O-31])
The data bus (DH[O-3]1 and DL[O-31]) consists of 64 signals that are both inputs and
outputs on the MPC750. Following are the state meaning and timing comments for the DH
and DL signals.
State Meaning
The data bus has two halves-data bus high (DH) and data bus low
(DL). See Table 7-4 for the data bus lane assignments.
Timing Comments The data bus is driven once for noncached transactions and four
times for cache transactions (bursts).
Table 7-4. Data Bus Lane Assignments
Data Bus Signals
Byte Lane
DH[Q-7]
0
DH[8-15]
1
DH[16-23]
2
DH[24-31]
3
DL[O-7]
4
DL[8-15]
5
DL[16-23]
6
DL[24-31]
7
7.2.7.1.1 Data Bus (DH[O-31], DL[O-31])-Output
Following are the state meaning and timing comments for the DH and DL output signals.
State Meaning
AssertedlNegated-Represents the state of data during a data write.
Byte lanes not selected for data transfer will not supply valid data.
Timing Comments Assertion/Negation-Initial beat coincides with DBB and, for
bursts, transitions on the bus clock cycle following each assertion of
TA.
High Impedance-Occurs on the bus clock cycle after the final
assertion ofTA, following the assertion of TEA, or in certain'ATR"'TrnR"'y"
cases.
Chapter 7. Signal Descriptions
7-17
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