Lcd Dram Dma Cycle 16-Bit Edo Ram Mode Access (Lcd Bus Master); Figure 19-11 Lcd Dram Dma Cycle 16-Bit Edo Ram Mode Access (Lcd Bus Master); Table 19-12 Lcd Sram/Rom Dma Cycle 16-Bit Mode Access Timing Parameters - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
Table 19-12. LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Parameters
Number
1 Address valid to CSx asserted
2 UWE/LWE to CSx asserted
3 Data setup time
4 CLKO to address valid
5 CLKO high to CSx
19.3.11 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access
(LCD Bus Master)
Figure 19-11 shows the timing diagram for the LCD DRAM DMA cycle for 16-bit EDO RAM mode
access (LCD bus master). The signal values and units of measure for this figure are found in Table 19-13
on page 19-15. Detailed information about the operation of individual signals can be found in Chapter 7,
"DRAM Controller," and Chapter 8, "LCD Controller."
MD[12:0]
RASx
CASx
DWE
OE
D[15:0]
Figure 19-11. LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)
19-14
Characteristic
Row Col 1
4
1
2
6
3 7
Timing Diagram
MC68VZ328 User's Manual
(3.0 ± 0.3) V
Minimum
20
28
16
—
—
Col 2 Col 3
8
5
11
10 12
14
9
7
13
Unit
Maximum
— ns
— ns
— ns
10 ns
10 ns