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to the DRAM bank. The PAL generates the RAS and CAS lines for the DRAM chips and con-
trols the address multiplexing in the external address buffers. One of the MC68000 chip-se-
lect lines can be used as the DRAM bank enable signal, if desired.
The refresh operation is a byte read operation. Thus, UDS or LDS will be asserted from the
MC68302, but not both. A refresh to an odd address will assert LDS; whereas, a refresh to
an even address will assert UDS.
MC68302
TOUT OR BRG
PB8
3.10.2 DRAM Refresh Controller Bus Timing
The DRAM refresh controller bus cycles are actually SDMA byte read accesses (see 4.2
SDMA Channels for more details). All timings, signals, and arbitration characteristics of
SDMA accesses apply to the DRAM refresh controller accesses. For example, DRAM re-
fresh cycles activate the BCLR signal, just like the SDMA. Note that the function code bits
may be used to distinguish DRAM refresh cycles from SDMA cycles, if desired.
A bus error on a DRAM refresh controller access causes the BERR channel number at offset
BASE + $67C to be written with a $0001. This is also the value written if the SCC1 receive
SDMA channel experiences a bus error; thus, these two sources cannot be distinguished
upon a bus error. The DRAM refresh SDMA channel and SCC1 receive SDMA channel are
separate and independent in all other respects.
3.10.3 Refresh Request Calculations
A typical 1-Mbyte DRAM needs one refresh cycle every 15.625 s. The DRAM refresh con-
troller is configured to execute one refresh cycle per request; thus, the PB8 pin should see
a high-to-low transition every 15.625 s. This is once every 260 cycles for a 16.67-MHz
clock. Note that one refresh per request minimizes the speed loss on the SCC channels.
MOTOROLA
DATA
Figure 3-13. DRAM Control Block Diagram
MC68302 USER'S MANUAL
System Integration Block (SIB)
CONTROL
ADDRESS
MUX
ADDRESS
BUFFERS
PAL
CONTROL
DRAM
BANK
3-67
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