Sdram Refresh Timing - Motorola DigitalDNA ColdFire MCF5272 User Manual

SDCLK
SDCLKE
SDADR[13:0]
A10_PRECHG
SDBA[1:0]
SDCS
RAS0
CAS0
SDWE
BS[3:0]
D[31:0]
Figure 9-12. SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1

9.10.3 SDRAM Refresh Timing

Figure 9-13 shows refresh-cycle timing. As in Figure 9-14, during a
command (T1), the SDRAM writes all of its on-chip RAM page buffers into the SDRAM
array. SDTR[RP] determines the number of dead cycles after a precharge. Note that self
refresh occurs during T3. In refresh state, SDRAM cannot accept any other command.
T0 T1 T2
CF2 Core
Page
Issue
Hit or
Address
Miss?
Chapter 9. SDRAM Controller
T3 T4 T5
Write Write
1 3
Write
2
Col Col Col
Bank
Data Data Data
SDRAM Interface
T6 T7 T8
Write
4
Col
Data
PRECHARGE ALL
9-21