Refresh/Scrub - Motorola MVME3600 Series Programmer's Reference Manual

Table 3-8. PowerPC 60 x to ROM/Flash Address Mapping when ROM/Flash is
64 Bits Wide (32 Bits per Falcon) (Continued)
PowerPC 60x A0-A31
$X3FFFFF3
$X3FFFFF4
$X3FFFFF5
$X3FFFFF6
$X3FFFFF7
$X3FFFFF8
$X3FFFFF9
$X3FFFFFA
$X3FFFFFB
$X3FFFFFC
$X3FFFFFD
$X3FFFFFE
$X3FFFFFF

Refresh/Scrub

Refresh/Scrub is done differently based on which DRAM blocks are
populated: (A and/or B) but not (C and D), or (A and/or B) and (C and/or
D).
Blocks A and/or B Present, Blocks C and D Not Present
The Falcon pair performs refresh by doing a burst of four RAS_ cycles
approximately once every 60µs. This increases to once every 30µs when
certain DRAM devices are used. (Controlled by the ram_fref bit in the
status registers.) RAS_ is asserted to both of Blocks A and B during each
of the 4 cycles. Along with RAS_, the Falcon pair also asserts CAS_ with
(OE_ then WE_) to one of the blocks during one of the four cycles. This
forms a read-modify-write which is a scrub cycle to that location.
After each of the 4 cycles, the DRAM row address increments by one.
When it reaches all 1's, it rolls over and starts over at 0. Each time the row
address rolls over, the block that is scrubbed toggles between A and B.
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ROM/Flash A22-A0
$7FFFFE
$7FFFFE
$7FFFFE
$7FFFFE
$7FFFFE
$7FFFFF
$7FFFFF
$7FFFFF
$7FFFFF
$7FFFFF
$7FFFFF
$7FFFFF
$7FFFFF
Functional Description
ROM/Flash Selected
Upper
Lower
Lower
Lower
Lower
Upper
Upper
Upper
Upper
Lower
Lower
Lower
Lower
3
3-19