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PLIC Registers
13.5.10 Periodic Status Registers (P0PSR–P3PSR)
All bits in these registers are read only and are set on hardware or software reset.
15
12
11
P0PSR–3
—
DTUE B2TUE B1TUE DROE B2ROE B1ROE DTDE B2TDE B1TDE DRDF B2RDE B1RDF
Reset
R/W
Addr
Figure 13-22. Periodic Status Registers (P0PSR–P3PSR)
PLPSRn are 16-bit registers containing the interrupt status information for the B- and
D-channel transmit and receive registers for each of the four ports on the MCF5272.
Bits
Name
15–12
—
11
DTUE
10
B2TUE
9
B1TUE
8
DROE
7
B2ROE
6
B1ROE
5
DTDE
13-24
10
9
8
MBAR + 0x384 (P0PSR); 0x386 (P1PSR); 0x388 (P2PSR); 0x38A (P3PSR)
Table 13-5. P0PSR–P3PSR Field Descriptions
Reserved, should be cleared.
D data transmit underrun error. This bit is set when the data in the PLTD transmit data
register for the respective port was transferred to the transmit shadow register, which was
already empty indicated by DTDE. DTUE is automatically cleared, when the PLPSR
register has been read by the CPU.
B2 data transmit underrun error. This bit is set when the data in the PLTB2 transmit data
register for the respective port was transferred to the transmit shadow register, which was
already empty indicated by B2TDE. B2TUE is automatically cleared when the PLPSR
register has been read by the CPU.
B1 data transmit underrun error. This bit is set when the data in the PLTB1 transmit data
register for the respective port was transferred to the transmit shadow register, which was
already empty indicated by B1TDE. B1TUE is automatically cleared when the PLPSR
register has been read by the CPU.
D-Channel data receive overrun error. This bit is set when the data in the D receive
shadow register for the respective port has been transferred to the receive data register
PLRD, which was already full indicated by DRDF. DROE is automatically cleared when the
PLPSR register has been read by the CPU.
B2 data receive overrun error. This bit is set when the data in the B2 receive shadow
register for the respective port has been transferred to the receive data register PLRB2,
which was already full indicated by B2RDF. B2ROE is automatically cleared when the
PLPSR register has been read by the CPU.
B1 data receive overrun error. This bit is set when the data in the B1 receive shadow
register for the respective port has been transferred to the receive data register PLRB1,
which was already full indicated by B1RDF. B1ROE is automatically cleared when the
PLPSR register has been read by the CPU. Note: Overrun and Underrun conditions are
caused by the B and/or D-channel receive or transmit data registers not being read or
written prior to a 2-KHz super frame arriving.
D data transmit data empty. This bit is set when the data in the PLTD transmit data register
for the respective port has been transferred to the transmit shadow register. This bit is
cleared when the CPU writes data to PLTD.
MCF5272 User's Manual
7
6
5
0000_0000_0000_0000
Read Only
Description
4
3
2
1
0
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