Rocketio X Transceiver Instantiations; Hdl Code Examples; Available Ports; Table 1-4: Primitive Ports - Xilinx RocketIO X User Manual

R
The RocketIO X transceiver consists of the Physical Media Attachment (PMA) and
Physical Coding Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES),
TX and RX buffers, clock generator, and clock recovery circuitry. The PCS contains the
8B/10B encoder/decoder, 64B/66B encoder/decoder/scrambler/descrambler, and the
elastic buffer supporting channel bonding and clock correction. Refer again to
page
signals.

RocketIO X Transceiver Instantiations

For the different clocking schemes, several things must change, including the clock
frequency for USRCLK and USRCLK2 discussed in
Domains."
widths. To implement the designs that do not take full advantage of the bus width,
concatenate zeros onto inputs and the wires for outputs for Verilog designs, and set
outputs to open and concatenate zeros on unused input bits for VHDL designs.

HDL Code Examples

The Architecture Wizard can be used to create instantiation templates. This wizard creates
code and instantiation templates that define the attributes for a specific application.

Available Ports

Table 1-4
primitives contain 72 ports. The differential serial data ports (RXN, RXP, TXN, and TXP)
are connected directly to external pads; the remaining 68 ports are all accessible from the
FPGA logic.

Table 1-4: Primitive Ports

Port
BREFCLKNIN
BREFCLKPIN
CHBONDDONE
CHBONDI[4:0]
CHBONDO[4:0]
ENCHANSYNC
28
26, showing the RocketIO X transceiver top-level block diagram and FPGA interface
The data and control ports for GT10_CUSTOM always use maximum bus
contains the port descriptions of all primitives. The RocketIO X transceiver
I/O Port Size
I 1 Differential BREFCLK negative input from the BREFCLK
pad. See
considerations.
I 1 Differential BREFCLK positive input from the BREFCLK
pad. See
considerations.
O 1 Indicates a receiver has successfully completed channel
bonding when asserted High.
I 5 The channel bonding control that is used only by "slaves"
which is driven by a transceiver's CHBONDO port. See
Figure
O 5 Channel bonding control that passes channel bonding and
clock correction control to other transceivers. See
Figure
I 1 Control from the fabric to the transceiver enables the
transceiver to perform channel bonding.
www.xilinx.com
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Chapter 1: RocketIO X Transceiver Overview
Chapter 3, "Clocking and Clock
Definition
Figure 4-31 and Figure 4-32
Figure 4-31 and Figure 4-32
2-10.
2-10.
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
Figure 1-1,
for analog
for analog