Rocketio Transceiver Instantiations; Hdl Code Examples - Xilinx RocketIO User Manual

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RocketIO Transceiver Instantiations

Table 1-4
attributes set to default values for the communications protocols listed in
widths of one, two, and four bytes are selectable for each protocol.
Table 1-4: Supported RocketIO Transceiver Primitives
GT_CUSTOM
GT_FIBRE_CHAN_1
GT_FIBRE_CHAN_2
GT_FIBRE_CHAN_4
GT_ETHERNET_1
GT_ETHERNET_2
GT_ETHERNET_4
GT_XAUI_1
There are two ways to modify the RocketIO transceiver:
•
•
The RocketIO transceiver consists of the Physical Media Attachment (PMA) and Physical
Coding Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES), TX and
RX buffers, clock generator, and clock recovery circuitry. The PCS contains the 8B/10B
encoder/decoder and the elastic buffer supporting channel bonding and clock correction.
The PCS also handles Cyclic Redundancy Check (CRC). Refer again to
the RocketIO transceiver top-level block diagram and FPGA interface signals.
RocketIO Transceiver Instantiations
For the different clocking schemes, several things must change, including the clock
frequency for USRCLK and USRCLK2 discussed in
Examples" in Chapter
change in data width by concatenating zeros onto inputs and wires for outputs for Verilog
designs, and by setting outputs to open and concatenating zeros on unused input bits for
VHDL designs.

HDL Code Examples

Please use the Architecture Wizard to create instantiation templates. This wizard creates
code and instantiation templates that define the attributes for a specific application.
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
lists the sixteen gigabit transceiver primitives provided. These primitives carry
Primitives Description
Fully customizable
by user
Fibre Channel,
1-byte data path
Fibre Channel,
2-byte data path
Fibre Channel,
4-byte data path
Gigabit Ethernet,
1-byte data path
Gigabit Ethernet,
2-byte data path
Gigabit Ethernet,
4-byte data path
10-Gb Ethernet,
1-byte data path
Static properties can be set through attributes in the HDL code. Use of attributes are
covered in detail in "Primitive Attributes," page
Dynamic changes can be made by the ports of the primitives
2. The data and control ports for GT_CUSTOM must also reflect this
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Primitive
10-Gb Ethernet,
GT_XAUI_2
2-byte data path
10-Gb Ethernet,
GT_XAUI_4
4-byte data path
Infiniband, 1-byte
GT_INFINIBAND_1
data path
Infiniband, 2-byte
GT_INFINIBAND_2
data path
Infiniband, 4-byte
GT_INFINIBAND_4
data path
Xilinx protocol,
GT_AURORA_1
1-byte data path
Xilinx protocol,
GT_AURORA_2
2-byte data path
Xilinx protocol,
GT_AURORA_4
4-byte data path
29.
Figure
"Digital Clock Manager (DCM)
R
Table 1-2. Data
Description
1-1, showing
23