Rocketio Transceiver Instantiations; Hdl Code Examples - Xilinx RocketIO User Manual

RocketIO Transceiver Instantiations

Table 1-4
set to default values for the communications protocols listed in
and four bytes are selectable for each protocol.
Table 1-4: Supported RocketIO Transceiver Primitives
There are two ways to modify the RocketIO transceiver:
•
•
The RocketIO transceiver consists of the Physical Media Attachment (PMA) and Physical Coding
Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES), TX and RX buffers, clock
generator, and clock recovery circuitry. The PCS contains the 8B/10B encoder/decoder and the
elastic buffer supporting channel bonding and clock correction. The PCS also handles Cyclic
Redundancy Check (CRC). Refer again to
block diagram and FPGA interface signals.
RocketIO Transceiver Instantiations
For the different clocking schemes, several things must change, including the clock frequency for
USRCLK and USRCLK2 discussed in
The data and control ports for GT_CUSTOM must also reflect this change in data width by
concatenating zeros onto inputs and wires for outputs for Verilog designs, and by setting outputs to
open and concatenating zeros on unused input bits for VHDL designs.

HDL Code Examples

Please use the Architecture Wizard to create instantiation templates. This wizard creates code and
instantiation templates that define the attributes for a specific application.
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
lists the sixteen gigabit transceiver primitives provided. These primitives carry attributes
Primitives
Fully customizable
GT_CUSTOM
by user
Fibre Channel,
GT_FIBRE_CHAN_1
1-byte data path
Fibre Channel,
GT_FIBRE_CHAN_2
2-byte data path
Fibre Channel,
GT_FIBRE_CHAN_4
4-byte data path
Gigabit Ethernet,
GT_ETHERNET_1
1-byte data path
Gigabit Ethernet,
GT_ETHERNET_2
2-byte data path
Gigabit Ethernet,
GT_ETHERNET_4
4-byte data path
10-Gb Ethernet,
GT_XAUI_1
1-byte data path
Static properties can be set through attributes in the HDL code. Use of attributes are covered in
detail in "Primitive Attributes," page
Dynamic changes can be made by the ports of the primitives
www.xilinx.com
1-800-255-7778
Description
GT_XAUI_2
GT_XAUI_4
GT_INFINIBAND_1
GT_INFINIBAND_2
GT_INFINIBAND_4
GT_AURORA_1
GT_AURORA_2
GT_AURORA_4
29.
Figure 1-1, showing the RocketIO transceiver top-level
"Digital Clock Manager (DCM) Examples" in Chapter
Table 1-2. Data widths of one, two,
Primitive Description
10-Gb Ethernet,
2-byte data path
10-Gb Ethernet,
4-byte data path
Infiniband, 1-byte
data path
Infiniband, 2-byte
data path
Infiniband, 4-byte
data path
Xilinx protocol,
1-byte data path
Xilinx protocol,
2-byte data path
Xilinx protocol,
4-byte data path
R
2.
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