Example 1A: Two-Byte Clock With Dcm - Xilinx RocketIO User Manual

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Clocking
Table 2-5: DCM Outputs for Different DATA_WIDTHs
TX_DATA_WIDTH
SERDES_10B
RX_DATA_WIDTH
FALSE
FALSE
FALSE
TRUE
TRUE
TRUE
Notes:
1. Since CLK0 is needed for feedback, it can be used instead of CLK180 to clock USRCLK or USRCLK2 of the transceiver with the use
of the transceiver's local inverter, saving a global buffer (BUFG).

Example 1a: Two-Byte Clock with DCM

The following HDL codes are examples of a simple clock scheme using 2-byte data with
both USRCLK and USRCLK2 at the same frequency. USRCLK_M is the input for both
USRCLK and USRCLK2.
Clocks for 2-Byte Data Path
VHDL Template
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
REFCLK
1 CLKIN
2 CLKIN
4 CLKIN
1 CLKIN
2 CLKIN
4 CLKIN
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
Figure 2-2: Two-Byte Clock with DCM
-- Module: TWO_BYTE_CLK
-- Description: VHDL submodule
-- DCM for 2-byte GT
--
-- Device: Virtex-II Pro Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity TWO_BYTE_CLK is
port (
REFCLKIN : in std_logic;
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TXUSRCLK
RXUSRCLK
CLK0
CLK0
(1)
CLK180
CLKDV (divide by 2)
CLKDV (divide by 2)
CLKFX180 (divide by 2)
MGT + DCM for 2-Byte Data Path
IBUFGDS
REFCLK_P
CLKIN
REFCLK_N
CLKFB
RST
TXUSRCLK2
RXUSRCLK2
CLK2X180
CLK0
CLKDV (divide by 2)
(1)
CLK180
CLKDV (divide by 2)
CLKDV (divide by 4)
GT_std_2
0
REFCLKSEL
DCM
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
CLK0
BUFG
ug024_02a_112202
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