Example 1: Two-Byte Clock; Figure 3-1: Two-Byte Clock - Xilinx RocketIO User Manual

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Example 1: Two-Byte Clock

The following HDL codes are examples of a simple clock scheme using 2-byte data with
both USRCLK and USRCLK2 at the same frequency. USRCLK_M is the input for both
USRCLK and USRCLK2.
Clocks for 2-Byte Data Path
VHDL Template
40
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2

Figure 3-1: Two-Byte Clock

-- Module: TWO_BYTE_CLK
-- Description: VHDL submodule
-- DCM for 2-byte GT
--
-- Device: Virtex-II Pro Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity TWO_BYTE_CLK is
port (
REFCLKIN : in std_logic;
RST : in std_logic;
USRCLK_M : out std_logic;
REFCLK : out std_logic;
LOCK : out std_logic
);
end TWO_BYTE_CLK;
--
architecture TWO_BYTE_CLK_arch of TWO_BYTE_CLK is
--
-- Components Declarations:
component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
--
component IBUFG
port (
I : in std_logic;
O : out std_logic
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Chapter 3: Digital Design Considerations
MGT + DCM for 2-Byte Data Path
IBUFG
DCM
REFCLK
CLKIN
CLKFB
RST
GT_std_2
0
REFCLKSEL
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
CLK0
BUFG
ug024_02_021102
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide