ST ST7LITEUS2 Manuals

Manuals and User Guides for ST ST7LITEUS2. We have 1 ST ST7LITEUS2 manual available for free PDF download: Quick Start Manual

ST ST7LITEUS2 Quick Start Manual (136 pages)

8-bit MCU with single voltage Flash memory, ADC, timers

Brand: ST | Category: Computer Hardware | Size: 1 MB

Table 1. Device Summary
1
Table of Contents
2
Introduction
11
Figure 1. General Block Diagram
11
Pin Description
12
Figure 2. 8-Pin so and Plastic DIP Package Pinout
12
Figure 3. 8-Pin DFN Package Pinout
12
Figure 4. 16-Pin Package Pinout
13
Table 2. Device Pin Description
14
Register and Memory Map
15
Figure 5. Memory Map
15
Table 3. Hardware Register Map
16
Flash Program Memory
18
Introduction
18
Main Features
18
Programming Modes
18
In-Circuit Programming (ICP)
18
In Application Programming (IAP)
19
I 2 C Interface
19
Memory Protection
20
Readout Protection
20
Figure 6. Typical I 2 C Interface
20
Flash Write/Erase Protection
21
Related Documentation
21
Register Description
22
Flash Control/Status Register (FCSR)
22
Table 4. FLASH Register Map and Reset Values
22
Central Processing Unit
23
Introduction
23
Main Features
23
CPU Registers
23
Accumulator (A)
23
Index Registers (X and Y)
23
Program Counter (PC)
23
Condition Code Register (CC)
24
Figure 7. CPU Registers
24
Stack Pointer (SP)
26
Figure 8. Stack Manipulation Example
27
Supply, Reset and Clock Management
28
Main Features
28
Internal RC Oscillator Adjustment
28
Table 5. Predefined RC Oscillator Calibration Values
28
Register Description
30
Main Clock Control/Status Register (MCCSR)
30
Figure 9. Clock Switching
30
RC Control Register (RCCR)
31
System Integrity (SI) Control/Status Register (SICSR)
31
AVD Threshold Selection Register (AVDTHCR)
32
Clock Controller Control/Status Register (CKCNTCSR)
32
Table 6. Internal RC Prescaler Selection Bits
32
Table 7. Clock Register Map and Reset Values
33
Figure 10. Clock Management Block Diagram
34
Reset Sequence Manager (RSM)
35
Introduction
35
Figure 11. Reset Sequence Phases
35
Asynchronous External RESET Pin
36
External Power-On Reset
36
Internal Low Voltage Detector (LVD) Reset
36
Figure 12. Reset Block Diagram
36
Internal Watchdog Reset
37
Register Description
37
Multiplexed I/O Reset Control Register 1 (MUXCR1)
37
Multiplexed I/O Reset Control Register 0 (MUXCR0)
37
Figure 13. Reset Sequences
37
Table 8. Multiplexed IO Register Map and Reset Values
38
Interrupts
39
Non Maskable Software Interrupt
39
External Interrupts
40
Peripheral Interrupts
40
Figure 14. Interrupt Processing Flowchart
40
External Interrupt Control Register 1 (EICR1)
41
Table 9. Interrupt Mapping
41
External Interrupt Control Register 2 (EICR2)
42
Table 10. Interrupt Sensitivity Bits
42
System Integrity Management (SI)
43
Low Voltage Detector (LVD)
43
Figure 15. Low Voltage Detector Vs Reset
44
Figure 16. Reset and Supply Management Block Diagram
44
Auxiliary Voltage Detector (AVD)
45
Figure 17. Using the AVD to Monitor VDD
45
Low Power Modes
46
Register Description
46
Table 11. Description of Low Power Modes
46
Table 12. Description of Interrupt Events
46
Table 13. System Integrity Register Map and Reset Values
47
Power Saving Modes
48
Introduction
48
Figure 18. Power Saving Mode Transitions
48
Slow Mode
49
Wait Mode
49
Figure 19. Slow Mode Clock Transition
49
Active-Halt and Halt Modes
50
Table 14. Enabling/Disabling Active-Halt and Halt Modes
50
Figure 20. Wait Mode Flowchart
50
Active-Halt Mode
51
Figure 21. Active-Halt Timing Overview
51
Halt Mode
52
Figure 22. Active-Halt Mode Flowchart
52
Figure 23. Halt Timing Overview
53
Figure 24. Halt Mode Flowchart
53
Auto-Wakeup from Halt Mode
54
Figure 25. AWUFH Mode Block Diagram
54
Figure 26. AWUF Halt Timing Diagram
55
Figure 27. AWUFH Mode Flowchart
56
Register Description
57
Table 15. Configuring the Dividing Factor
58
Table 16. AWU Register Map and Reset Values
58
I/O Ports
59
Introduction
59
Functional Description
59
Input Modes
59
Output Modes
60
Table 17. DR Register Value and Output Pin Status
60
Alternate Functions
61
Figure 28. I/O Port General Block Diagram
61
Table 18. I/O Port Mode Options
62
Table 19. I/O Port Configurations
62
Unused I/O Pins
63
Low Power Modes
63
Interrupts
63
Table 20. Effect of Low Power Modes on I/O Ports
63
Table 21. Description of Interrupt Events
63
I/O Port Implementation
64
Table 22. Port Configuration
64
Table 23. I/O Port Register Map and Reset Values
64
Figure 29. Interrupt I/O Port State Transitions
64
On-Chip Peripherals
65
Lite Timer (LT)
65
Introduction
65
Main Features
65
Functional Description
66
Figure 30. Lite Timer Block Diagram
66
Figure 31. Watchdog Timing Diagram
67
Low Power Modes
68
Interrupts
68
Table 24. Description of Low Power Modes
68
Table 25. Interrupt Events
68
Figure 32. Input Capture Timing Diagram
68
Register Description
69
Table 26. Lite Timer Register Map and Reset Values
70
12-Bit Auto-Reload Timer (AT)
71
Introduction
71
Main Features
71
Functional Description
71
Figure 33. Block Diagram
71
Figure 34. PWM Function
72
Low Power Modes
73
Table 27. Description of Low Power Modes
73
Figure 35. PWM Signal Example
73
Interrupts
74
Register Description
74
Table 28. Interrupt Events
74
Table 29. Counter Clock Selection
75
Table 30. Register Map and Reset Values
77
10-Bit A/D Converter (ADC)
79
Introduction
79
Main Features
79
Functional Description
79
Figure 36. ADC Block Diagram
80
Low Power Modes
81
Table 31. Effect of Low Power Modes
81
Interrupts
82
Register Description
82
Table 32. Channel Selection
82
Table 33. Configuring the ADC Clock Speed
83
Table 34. ADC Register Map and Reset Values
83
Instruction Set
84
ST7 Addressing Modes
84
Table 35. Description of Addressing Modes
84
Table 36. ST7 Addressing Mode Overview
84
Inherent Mode
85
Table 37. Instructions Supporting Inherent Addressing Mode
85
Immediate
86
Direct
86
Indexed Mode (no Offset, Short, Long)
86
Table 38. Instructions Supporting Inherent Immediate Addressing Mode
86
Indirect Modes (Short, Long)
87
Indirect Indexed Modes (Short, Long)
87
Table 39. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
87
Relative Modes (Direct, Indirect)
88
Instruction Groups
88
Table 40. Instructions Supporting Relative Modes
88
Table 41. ST7 Instruction Set
88
Illegal Opcode Reset
89
Table 42. Illegal Opcode Detection
89
Electrical Characteristics
92
Parameter Conditions
92
Minimum and Maximum Values
92
Typical Values
92
Typical Curves
92
Loading Capacitor
92
Figure 37. Pin Loading Conditions
92
Pin Input Voltage
93
Absolute Maximum Ratings
93
Table 43. Voltage Characteristics
93
Figure 38. Pin Input Voltage
93
Operating Conditions
94
General Operating Conditions
94
Table 44. Current Characteristics
94
Table 45. Thermal Characteristics
94
Table 46. General Operating Conditions
94
Operating Conditions with Low Voltage Detector (LVD)
95
Table 47. Operating Characteristics with LVD
95
Figure 39. Fcpu Maximum Operating Frequency Versus
95
Auxiliary Voltage Detector (AVD) Thresholds
96
Internal RC Oscillator
96
Table 48. Operating Characteristics with AVD
96
Table 49. Voltage Drop between AVD Flag Set and LVD Reset Generation
96
Table 50. Internal RC Oscillator Characteristics (5.0 V Calibration)
97
Table 51. Internal RC Oscillator Characteristics (3.3 V Calibration)
97
Figure 40. Typical Accuracy with RCCR=RCCR0 Vs VDD= 2.4-6.0 V and Temperature
98
Figure 41. Typical Accuracy with RCCR=RCCR1 Vs VDD= 2.4-6.0V and Temperature
98
Supply Current Characteristics
99
Supply Current
99
Table 52. Supply Current Characteristics
99
Internal RC Oscillator Supply Current Characteristics
100
Table 53. Internal RC Oscillator Supply Current
100
Figure 42. Typical IDD in Run Mode Vs. Internal Clock Frequency and VDD
101
Figure 43. Typical IDD in WFI Mode Vs. Internal Clock Frequency and VDD
101
Figure 45. IDD Vs Temp @VDD 5 V & Int RC = 8 Mhz
102
Figure 46. IDD Vs Temp @VDD 5 V & Int RC = 4 Mhz
102
Figure 47. IDD Vs Temp @VDD 5 V & Int RC = 2 Mhz
102
On-Chip Peripherals
103
Clock and Timing Characteristics
103
Table 54. On-Chip Peripheral Characteristics
103
Table 55. General Timings
103
Table 56. Auto-Wakeup RC Oscillator
103
Memory Characteristics
104
Table 57. RAM and Hardware Registers
104
Table 58. Flash Program Memory
104
EMC Characteristics
105
Functional EMS (Electromagnetic Susceptibility)
105
Table 59. EMC Characteristics
105
Electromagnetic Interference (EMI)
106
Absolute Maximum Ratings (Electrical Sensitivity)
106
Table 60. EMI Characteristics
106
Table 61. Absolute Maximum Ratings
106
Table 62. Electrical Sensitivities
107
I/O Port Pin Characteristics
108
General Characteristics
108
Table 63. General Characteristics
108
Figure 48. Two Typical Applications with Unused I/O Pin
108
Output Driving Current Characteristics
109
Table 64. Output Driving Current Characteristics
109
Figure 49. Typical IPU Vs. VDD with Vin=Vssl
109
Figure 50. Typical VOL at VDD = 2.4 V (Standard Pins)
110
Figure 51. Typical VOL at VDD = 3 V (Standard Pins)
110
Figure 52. Typical VOL at VDD = 5 V (Standard Pins)
110
Figure 53. Typical VOL at VDD = 2.4 V (HS Pins)
111
Figure 54. Typical VOL at VDD = 3 V (HS Pins)
111
Figure 55. Typical VOL at VDD = 5 V (HS Pins)
111
Figure 56. Typical VDD-VOH at VDD = 2.4 V (HS Pins)
112
Figure 57. Typical VDD-VOH at VDD = 3 V (HS Pins)
112
Figure 58. Typical VDD-VOH at VDD = 5 V (HS Pins)
112
Control Pin Characteristics
113
Figure 59. Typical VOL Vs. VDD (HS Pins)
113
Figure 60. Typical VDD-VOH Vs. VDD (HS Pins)
113
Table 65. Asynchronous RESET Pin Characteristics
114
Figure 61. RESET Pin Protection When LVD Is Enabled
114
ADC Characteristics
115
Table 66. 10-Bit ADC Characteristics
115
Figure 62. RESET Pin Protection When LVD Is Disabled
115
Table 67. ADC Accuracy with VDD = 3.3 to 5.5 V
116
Table 68. ADC Accuracy with VDD = 2.7 to 3.3 V
116
Table 69. ADC Accuracy with VDD = 2.4V to 2.7V
116
Figure 63. Typical Application with ADC
116
Figure 64. ADC Accuracy Characteristics
117
Package Characteristics
118
Package Mechanical Data
118
Table 70. 8-Lead very Thin Fine Pitch Dual Flat No-Lead Package Mechanical Data
118
Figure 65. 8-Lead very Thin Fine Pitch Dual Flat No-Lead Package Outline
118
Table 71. 8-Pin Plastic Small Outline Package, 150-Mil Width, Package Mechanical
119
Figure 66. 8-Pin Plastic Small Outline Package, 150-Mil Width Package Outline
119
Table 72. 8-Pin Plastic Dual In-Line Package, 300-Mil Width Package Mechanical Data
120
Figure 67. 8-Pin Plastic Dual In-Line Package, 300-Mil Width Package Outline
120
Table 73. 16-Pin Plastic Dual In-Line Package, 300-Mil Width, Package Mechanical
121
Figure 68. 16-Pin Plastic Dual In-Line Package, 300-Mil Width, Package Outline
121
Thermal Characteristics
122
Table 74. Thermal Characteristics
122
Device Configuration and Ordering Information
123
Option Bytes
123
Option Byte 1
123
Option Byte 0
124
Table 75. Startup Clock Selection
124
Table 76. LVD Threshold Configuration
124
Table 77. Definition of Sector 0 Size
124
Ordering Information
125
Table 79. Supported Order Codes
125
Figure 69. Option List
127
Development Tools
128
Starter Kits
128
Development and Debugging Tools
128
Programming Tools
128
Order Codes for Development and Programming Tools
128
ST7 Application Notes
129
Table 80. Development Tool Order Codes for the St7Liteusx Family
129
Table 81. ST7 Application Notes
129
Known Limitations
133
Revision History
134
Table 82. Document Revision History
134

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