Interrupts And Events; Nested Vectored Interrupt Controller (Nvic); Systick Calibration Value Register; Interrupt And Exception Vectors - ST STM32F101 Series Reference Manual

Interrupts and events

6 Interrupts and events
6.1

Nested vectored interrupt controller (NVIC)

Features
43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)
16 programmable priority levels (4 bits of interrupt priority are used)
Low-latency exception and interrupt handling
Power management control
Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming see Chap 5 Exceptions & Chap 8 Nested Vectored
Interrupt Controller of the ARM Cortex™-M3 Technical Reference Manual.
6.1.1

SysTick calibration value register

The SysTick calibration value is fixed to 9000 which allows the generation of a time base of
1ms with the SysTick clock set to 9 MHz (max HCLK/8).
6.1.2

Interrupt and exception vectors

Table 27.
-
-3
-2
-1
0
1
2
-
3
4
-
5
98/501
Vector table
Type of
Acronym
priority
- -
fixed Reset
fixed NMI
fixed HardFault
settable MemManage
settable BusFault
settable UsageFault
- -
settable SVCall
settable Debug Monitor
- -
settable PendSV
Description
Reserved
Reset
Non maskable interrupt. The RCC
Clock Security System (CSS) is linked
to the NMI vector.
All class of fault
Memory management
Pre-fetch fault, memory access fault
Undefined instruction or illegal state
Reserved
System service call via SWI
instruction
Debug Monitor
Reserved
Pendable request for system service
RM0008
Address
0x0000_0000
0x0000_0004
0x0000_0008
0x0000_000C
0x0000_0010
0x0000_0014
0x0000_0018
0x0000_001C -
0x0000_002B
0x0000_002C
0x0000_0030
0x0000_0034
0x0000_0038