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ST STM32F3 Series Manuals
Manuals and User Guides for ST STM32F3 Series. We have
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ST STM32F3 Series manuals available for free PDF download: Programming Manual, Application Note
ST STM32F3 Series Programming Manual (260 pages)
Cortex-M4
Brand:
ST
| Category:
Computer Hardware
| Size: 3 MB
Table of Contents
Reference Documents
1
Table of Contents
2
About this Document
12
Typographical Conventions
12
List of Abbreviations for Registers
12
About the STM32 Cortex-M4 Processor and Core Peripherals
13
Figure 1. STM32 Cortex-M4 Implementation
13
Cortex-M4 Processor Features and Benefits Summary
14
Integrated Configurable Debug
14
System Level Interface
14
Cortex-M4 Core Peripherals
15
The Cortex-M4 Processor
16
Programmers Model
16
Processor Mode and Privilege Levels for Software Execution
16
Stacks
16
Core Registers
17
Figure 2. Processor Core Registers
17
Table 1. Summary of Processor Mode, Execution Privilege Level, and Stack Usage
17
Table 2. Core Register Set Summary
17
Program Counter
18
Program Status Register
18
Stack Pointer
18
Table 3. PSR Register Combinations
19
Figure 3. APSR, IPSR and EPSR Bit Assignments
19
Figure 4. PSR Bit Assignments
19
Table 4. APSR Bit Definitions
20
Table 5. IPSR Bit Definitions
21
Table 6. EPSR Bit Definitions
22
Table 7. PRIMASK Register Bit Definitions
23
Table 8. FAULTMASK Register Bit Definitions
23
Figure 5. PRIMASK Bit Assignments
23
Figure 6. FAULTMASK Bit Assignments
23
Table 9. BASEPRI Register Bit Assignments
24
Table 10. CONTROL Register Bit Definitions
24
Figure 7. BASEPRI Bit Assignments
24
Exceptions and Interrupts
25
Data Types
25
The Cortex Microcontroller Software Interface Standard (CMSIS)
25
Memory Model
27
Figure 8. Memory Map
27
Memory Regions, Types and Attributes
28
Memory System Ordering of Memory Accesses
28
Table 11. Ordering of Memory Accesses
28
Behavior of Memory Accesses
29
Table 12. Memory Access Behavior
29
Software Ordering of Memory Accesses
30
Bit-Banding
31
Table 13. SRAM Memory Bit-Banding Regions
31
Table 14. Peripheral Memory Bit-Banding Regions
31
Figure 9. Bit-Band Mapping
32
Figure 10. Little-Endian Example
33
Memory Endianness
33
Synchronization Primitives
33
Programming Hints for the Synchronization Primitives
35
Table 15. CMSIS Functions for Exclusive Access Instructions
35
Exception Model
36
Exception States
36
Exception Types
36
Table 16. Properties of the Different Exception Types
37
Exception Handlers
38
Vector Table
39
Figure 11. Vector Table
39
Exception Priorities
40
Interrupt Priority Grouping
40
Exception Entry and Return
41
Figure 12. Cortex-M4 Stack Frame Layout
42
Fault Handling
43
Table 17. Exception Return Behavior
43
Fault Types
44
Table 18. Faults
44
Fault Escalation and Hard Faults
45
Fault Status Registers and Fault Address Registers
46
Lockup
46
Power Management
46
Table 19. Fault Status and Fault Address Registers
46
Entering Sleep Mode
47
Wakeup from Sleep Mode
47
External Event Input / Extended Interrupt and Event Input
48
Power Management Programming Hints
48
The STM32 Cortex-M4 Instruction Set
49
Instruction Set Summary
49
Table 20. Cortex-M4 Instructions
49
CMSIS Intrinsic Functions
57
Table 21. CMSIS Intrinsic Functions to Generate some Cortex-M4 Instructions
58
Table 22. CMSIS Intrinsic Functions to Access the Special Registers
58
About the Instruction Descriptions
59
Operands
59
Restrictions When Using PC or SP
59
Flexible Second Operand
59
Shift Operations
61
Figure 13. ASR #3
61
Figure 14. LSR #3
62
Figure 15. LSL #3
62
Figure 16. ROR #3
63
Figure 17. RRX #3
63
Address Alignment
64
PC-Relative Expressions
64
Conditional Execution
64
Table 23. Condition Code Suffixes
66
Instruction Width Selection
67
Memory Access Instructions
68
Table 24. Memory Access Instructions
68
Adr
69
LDR and STR, Immediate Offset
70
Table 25. Immediate, Pre-Indexed and Post-Indexed Offset Ranges
71
LDR and STR, Register Offset
72
LDR and STR, Unprivileged
73
LDR, PC-Relative
74
Table 26. Label-PC Offset Ranges
74
LDM and STM
75
PUSH and POP
77
LDREX and STREX
78
Clrex
79
General Data Processing Instructions
80
Table 27. Data Processing Instructions
80
ADD, ADC, SUB, SBC, and RSB
82
AND, ORR, EOR, BIC, and ORN
84
ASR, LSL, LSR, ROR, and RRX
85
Clz
86
CMP and CMN
87
MOV and MVN
88
Movt
90
REV, REV16, REVSH, and RBIT
91
SADD16 and SADD8
92
SHADD16 and SHADD8
93
SHASX and SHSAX
94
SHSUB16 and SHSUB8
95
SSUB16 and SSUB8
96
SASX and SSAX
97
TST and TEQ
98
UADD16 and UADD8
99
UASX and USAX
100
UHADD16 and UHADD8
101
UHASX and UHSAX
102
UHSUB16 and UHSUB8
103
Sel
104
Usad8
105
Usada8
106
USUB16 and USUB8
107
Multiply and Divide Instructions
108
Table 28. Multiply and Divide Instructions
108
MUL, MLA, and MLS
109
UMULL, UMAAL and UMLAL
110
SMLA and SMLAW
111
Smlad
113
SMLAL and SMLALD
114
SMLSD and SMLSLD
116
SMMLA and SMMLS
118
Smmul
119
SMUAD and SMUSD
120
SMUL and SMULW
121
UMULL, UMLAL, SMULL, and SMLAL
122
SDIV and UDIV
123
Saturating Instructions
124
Table 29. Saturating Instructions
124
SSAT and USAT
125
SSAT16 and USAT16
126
QADD and QSUB
127
QASX and QSAX
128
QDADD and QDSUB
129
UQASX and UQSAX
130
UQADD and UQSUB
131
Packing and Unpacking Instructions
133
Table 30. Packing and Unpacking Instructions
133
PKHBT and PKHTB
134
SXT and UXT
135
SXTA and UXTA
136
Bitfield Instructions
137
Table 31. Instructions that Operate on Adjacent Sets of Bits
137
BFC and BFI
138
SBFX and UBFX
139
SXT and UXT
140
B, BL, BX, and BLX
141
Branch and Control Instructions
141
Table 32. Branch and Control Instructions
141
Table 33. Branch Ranges
142
CBZ and CBNZ
143
TBB and TBH
146
Floating-Point Instructions
148
Table 34. Floating-Point Instructions
148
Vabs
150
Vadd
151
Vcmp, Vcmpe
152
VCVT, VCVTR between Floating-Point and Integer
153
VCVT between Floating-Point and Fixed-Point
154
Vcvtb, Vcvtt
155
VDIV
156
Vfma, Vfms
157
Vfnma, Vfnms
158
Vldm
159
Vldr
160
Vlma, Vlms
161
VMOV Immediate
162
VMOV Register
163
VMOV Scalar to ARM Core Register
164
VMOV ARM Core Register to Single Precision
165
VMOV Two ARM Core Registers to Two Single Precision
166
VMOV ARM Core Register to Scalar
167
Vmrs
168
Vmsr
169
Vmul
170
Vneg
171
Vnmla, Vnmls, Vnmul
172
Vpop
173
Vpush
174
Vsqrt
175
Vstm
176
Vstr
177
Vsub
178
Miscellaneous Instructions
179
Table 35. Miscellaneous Instructions
179
Bkpt
180
Cps
181
Dmb
182
Dsb
183
Isb
184
Mrs
185
Msr
186
Nop
187
Sev
188
Svc
189
Wfe
190
Wfi
191
Advertisement
ST STM32F3 Series Programming Manual (262 pages)
Brand:
ST
| Category:
Computer Hardware
| Size: 2 MB
Table of Contents
Table 1. Applicable Products
1
Table of Contents
2
About this Document
12
Typographical Conventions
12
List of Abbreviations for Registers
12
About the STM32 Cortex-M4 Processor and Core Peripherals
13
Figure 1. STM32 Cortex-M4 Implementation
13
Integrated Configurable Debug
14
System Level Interface
14
Cortex-M4 Processor Features and Benefits Summary
15
Cortex-M4 Core Peripherals
16
The Cortex-M4 Processor
17
Programmers Model
17
Processor Mode and Privilege Levels for Software Execution
17
Stacks
17
Core Registers
18
Table 2. Summary of Processor Mode, Execution Privilege Level, and Stack Usage
18
Table 3. Core Register Set Summary
18
Figure 2. Processor Core Registers
18
Table 4. PSR Register Combinations
20
Figure 3. APSR, IPSR and EPSR Bit Assignment
20
Figure 4. PSR Bit Assignment
20
Table 5. APSR Bit Definitions
21
Table 6. IPSR Bit Definitions
22
Table 7. EPSR Bit Definitions
23
Table 8. PRIMASK Register Bit Definitions
24
Table 9. FAULTMASK Register Bit Definitions
24
Figure 5. PRIMASK Bit Assignment
24
Figure 6. FAULTMASK Bit Assignment
24
Table 10. BASEPRI Register Bit Assignment
25
Table 11. CONTROL Register Bit Definitions
25
Figure 7. BASEPRI Bit Assignment
25
Exceptions and Interrupts
26
Data Types
26
The Cortex Microcontroller Software Interface Standard (CMSIS)
26
Memory Model
28
Figure 8. Memory Map
28
Memory Regions, Types and Attributes
29
Memory System Ordering of Memory Accesses
29
Table 12. Ordering of Memory Accesses
29
Behavior of Memory Accesses
30
Table 13. Memory Access Behavior
30
Software Ordering of Memory Accesses
31
Bit-Banding
32
Table 14. SRAM Memory Bit-Banding Regions
32
Table 15. Peripheral Memory Bit-Banding Regions
32
Figure 9. Bit-Band Mapping
33
Figure 10. Little-Endian Example
34
Memory Endianness
34
Synchronization Primitives
34
Programming Hints for the Synchronization Primitives
36
Table 16. CMSIS Functions for Exclusive Access Instructions
36
Exception Model
37
Exception States
37
Exception Types
37
Table 17. Properties of the Different Exception Types
38
Exception Handlers
39
Vector Table
40
Figure 11. Vector Table
40
Exception Priorities
41
Interrupt Priority Grouping
41
Exception Entry and Return
42
Figure 12. Cortex-M4 Stack Frame Layout
43
Fault Handling
44
Table 18. Exception Return Behavior
44
Fault Types
45
Table 19. Faults
45
Fault Escalation and Hard Faults
46
Fault Status Registers and Fault Address Registers
47
Lockup
47
Power Management
47
Table 20. Fault Status and Fault Address Registers
47
Entering Sleep Mode
48
Wakeup from Sleep Mode
48
External Event Input / Extended Interrupt and Event Input
49
Power Management Programming Hints
49
The STM32 Cortex-M4 Instruction Set
50
Instruction Set Summary
50
Table 21. Cortex-M4 Instructions
50
CMSIS Intrinsic Functions
58
Table 22. CMSIS Intrinsic Functions to Generate some Cortex-M4 Instructions
59
Table 23. CMSIS Intrinsic Functions to Access the Special Registers
59
About the Instruction Descriptions
60
Operands
60
Restrictions When Using PC or SP
60
Flexible Second Operand
60
Shift Operations
62
Figure 13. ASR #3
62
Figure 14. LSR #3
63
Figure 15. LSL #3
63
Figure 16. ROR #3
64
Figure 17. RRX #3
64
Address Alignment
65
PC-Relative Expressions
65
Conditional Execution
65
Table 24. Condition Code Suffixes
67
Instruction Width Selection
68
Memory Access Instructions
69
Table 25. Memory Access Instructions
69
Adr
70
LDR and STR, Immediate Offset
71
Table 26. Immediate, Pre-Indexed and Post-Indexed Offset Ranges
72
LDR and STR, Register Offset
73
LDR and STR, Unprivileged
74
LDR, PC-Relative
75
Table 27. Label-PC Offset Ranges
75
LDM and STM
76
PUSH and POP
78
LDREX and STREX
79
Clrex
80
General Data Processing Instructions
81
Table 28. Data Processing Instructions
81
ADD, ADC, SUB, SBC, and RSB
83
AND, ORR, EOR, BIC, and ORN
85
ASR, LSL, LSR, ROR, and RRX
86
Clz
87
CMP and CMN
88
MOV and MVN
89
Movt
91
REV, REV16, REVSH, and RBIT
92
SADD16 and SADD8
93
SHADD16 and SHADD8
94
SHASX and SHSAX
95
SHSUB16 and SHSUB8
96
SSUB16 and SSUB8
97
SASX and SSAX
98
TST and TEQ
99
UADD16 and UADD8
100
UASX and USAX
101
UHADD16 and UHADD8
102
UHASX and UHSAX
103
UHSUB16 and UHSUB8
104
Sel
105
Usad8
106
Usada8
107
USUB16 and USUB8
108
Multiply and Divide Instructions
109
Table 29. Multiply and Divide Instructions
109
MUL, MLA, and MLS
110
UMULL, UMAAL and UMLAL
111
SMLA and SMLAW
112
Smlad
114
SMLAL and SMLALD
115
SMLSD and SMLSLD
117
SMMLA and SMMLS
119
Smmul
120
SMUAD and SMUSD
121
SMUL and SMULW
122
UMULL, UMLAL, SMULL, and SMLAL
123
SDIV and UDIV
124
Saturating Instructions
125
Table 30. Saturating Instructions
125
SSAT and USAT
126
SSAT16 and USAT16
127
QADD and QSUB
128
QASX and QSAX
129
QDADD and QDSUB
130
UQASX and UQSAX
131
UQADD and UQSUB
132
Packing and Unpacking Instructions
134
Table 31. Packing and Unpacking Instructions
134
PKHBT and PKHTB
135
SXT and UXT
136
SXTA and UXTA
137
Bitfield Instructions
138
Table 32. Instructions that Operate on Adjacent Sets of Bits
138
BFC and BFI
139
SBFX and UBFX
140
SXT and UXT
141
B, BL, BX, and BLX
142
Branch and Control Instructions
142
Table 33. Branch and Control Instructions
142
Table 34. Branch Ranges
143
CBZ and CBNZ
144
TBB and TBH
147
Floating-Point Instructions
149
Table 35. Floating-Point Instructions
149
Vabs
151
Vadd
152
Vcmp, Vcmpe
153
VCVT, VCVTR between Floating-Point and Integer
154
VCVT between Floating-Point and Fixed-Point
155
Vcvtb, Vcvtt
156
VDIV
157
Vfma, Vfms
158
Vfnma, Vfnms
159
Vldm
160
Vldr
161
Vlma, Vlms
162
VMOV Immediate
163
VMOV Register
164
VMOV Scalar to Arm Core Register
165
VMOV Arm Core Register to Single Precision
166
VMOV Two Arm Core Registers to Two Single Precision
167
VMOV Arm Core Register to Scalar
168
Vmrs
169
Vmsr
170
Vmul
171
Vneg
172
Vnmla, Vnmls, Vnmul
173
Vpop
174
Vpush
175
Vsqrt
176
Vstm
177
Vstr
178
Vsub
179
Miscellaneous Instructions
180
Table 36. Miscellaneous Instructions
180
Bkpt
181
Cps
182
Dmb
183
Dsb
184
Isb
185
Mrs
186
Msr
187
Nop
188
Sev
189
Svc
190
Wfe
191
Wfi
192
ST STM32F3 Series Programming Manual (262 pages)
Brand:
ST
| Category:
Computer Hardware
| Size: 2 MB
Table of Contents
Table 1. Applicable Products
1
Table of Contents
2
About this Document
12
Typographical Conventions
12
List of Abbreviations for Registers
12
About the STM32 Cortex-M4 Processor and Core Peripherals
13
Figure 1. STM32 Cortex-M4 Implementation
13
System Level Interface
14
Integrated Configurable Debug
14
Cortex-M4 Processor Features and Benefits Summary
15
Cortex-M4 Core Peripherals
16
The Cortex-M4 Processor
17
Programmers Model
17
Processor Mode and Privilege Levels for Software Execution
17
Stacks
17
Core Registers
18
Table 2. Summary of Processor Mode, Execution Privilege Level, and Stack Usage
18
Table 3. Core Register Set Summary
18
Figure 2. Processor Core Registers
18
Table 4. PSR Register Combinations
20
Figure 3. APSR, IPSR and EPSR Bit Assignment
20
Figure 4. PSR Bit Assignment
20
Table 5. APSR Bit Definitions
21
Table 6. IPSR Bit Definitions
22
Table 7. EPSR Bit Definitions
23
Table 8. PRIMASK Register Bit Definitions
24
Table 9. FAULTMASK Register Bit Definitions
24
Figure 5. PRIMASK Bit Assignment
24
Figure 6. FAULTMASK Bit Assignment
24
Table 10. BASEPRI Register Bit Assignment
25
Table 11. CONTROL Register Bit Definitions
25
Figure 7. BASEPRI Bit Assignment
25
Exceptions and Interrupts
26
Data Types
26
The Cortex Microcontroller Software Interface Standard (CMSIS)
26
Memory Model
28
Figure 8. Memory Map
28
Memory Regions, Types and Attributes
29
Memory System Ordering of Memory Accesses
29
Table 12. Ordering of Memory Accesses
29
Behavior of Memory Accesses
30
Table 13. Memory Access Behavior
30
Software Ordering of Memory Accesses
31
Bit-Banding
32
Table 14. SRAM Memory Bit-Banding Regions
32
Table 15. Peripheral Memory Bit-Banding Regions
32
Figure 9. Bit-Band Mapping
33
Memory Endianness
34
Synchronization Primitives
34
Figure 10. Little-Endian Example
34
Programming Hints for the Synchronization Primitives
36
Table 16. CMSIS Functions for Exclusive Access Instructions
36
Exception Model
37
Exception States
37
Exception Types
37
Table 17. Properties of the Different Exception Types
38
Exception Handlers
39
Vector Table
40
Figure 11. Vector Table
40
Exception Priorities
41
Interrupt Priority Grouping
41
Exception Entry and Return
42
Figure 12. Cortex-M4 Stack Frame Layout
43
Fault Handling
44
Table 18. Exception Return Behavior
44
Fault Types
45
Table 19. Faults
45
Fault Escalation and Hard Faults
46
Fault Status Registers and Fault Address Registers
47
Lockup
47
Power Management
47
Table 20. Fault Status and Fault Address Registers
47
Entering Sleep Mode
48
Wakeup from Sleep Mode
48
External Event Input / Extended Interrupt and Event Input
49
Power Management Programming Hints
49
The STM32 Cortex-M4 Instruction Set
50
Instruction Set Summary
50
Table 21. Cortex-M4 Instructions
50
CMSIS Intrinsic Functions
58
Table 22. CMSIS Intrinsic Functions to Generate some Cortex-M4 Instructions
59
Table 23. CMSIS Intrinsic Functions to Access the Special Registers
59
About the Instruction Descriptions
60
Operands
60
Restrictions When Using PC or SP
60
Flexible Second Operand
60
Shift Operations
62
Figure 13. ASR #3
62
Figure 14. LSR #3
63
Figure 15. LSL #3
63
Figure 16. ROR #3
64
Figure 17. RRX #3
64
Address Alignment
65
PC-Relative Expressions
65
Conditional Execution
65
Table 24. Condition Code Suffixes
67
Instruction Width Selection
68
Memory Access Instructions
69
Table 25. Memory Access Instructions
69
Adr
70
LDR and STR, Immediate Offset
71
Table 26. Immediate, Pre-Indexed and Post-Indexed Offset Ranges
72
LDR and STR, Register Offset
73
LDR and STR, Unprivileged
74
LDR, PC-Relative
75
Table 27. Label-PC Offset Ranges
75
LDM and STM
76
PUSH and POP
78
LDREX and STREX
79
Clrex
80
General Data Processing Instructions
81
Table 28. Data Processing Instructions
81
ADD, ADC, SUB, SBC, and RSB
83
AND, ORR, EOR, BIC, and ORN
85
ASR, LSL, LSR, ROR, and RRX
86
Clz
87
CMP and CMN
88
MOV and MVN
89
Movt
91
REV, REV16, REVSH, and RBIT
92
SADD16 and SADD8
93
SHADD16 and SHADD8
94
SHASX and SHSAX
95
SHSUB16 and SHSUB8
96
SSUB16 and SSUB8
97
SASX and SSAX
98
TST and TEQ
99
UADD16 and UADD8
100
UASX and USAX
101
UHADD16 and UHADD8
102
UHASX and UHSAX
103
UHSUB16 and UHSUB8
104
Sel
105
Usad8
106
Usada8
107
USUB16 and USUB8
108
Multiply and Divide Instructions
109
Table 29. Multiply and Divide Instructions
109
MUL, MLA, and MLS
110
UMULL, UMAAL and UMLAL
111
SMLA and SMLAW
112
Smlad
114
SMLAL and SMLALD
115
SMLSD and SMLSLD
117
SMMLA and SMMLS
119
Smmul
120
SMUAD and SMUSD
121
SMUL and SMULW
122
UMULL, UMLAL, SMULL, and SMLAL
123
SDIV and UDIV
124
Saturating Instructions
125
Table 30. Saturating Instructions
125
SSAT and USAT
126
SSAT16 and USAT16
127
QADD and QSUB
128
QASX and QSAX
129
QDADD and QDSUB
130
UQASX and UQSAX
131
UQADD and UQSUB
132
Packing and Unpacking Instructions
134
Table 31. Packing and Unpacking Instructions
134
PKHBT and PKHTB
135
SXT and UXT
136
SXTA and UXTA
137
Bitfield Instructions
138
Table 32. Instructions that Operate on Adjacent Sets of Bits
138
BFC and BFI
139
SBFX and UBFX
140
SXT and UXT
141
Branch and Control Instructions
142
B, BL, BX, and BLX
142
Table 33. Branch and Control Instructions
142
Table 34. Branch Ranges
143
CBZ and CBNZ
144
TBB and TBH
147
Floating-Point Instructions
149
Table 35. Floating-Point Instructions
149
Vabs
151
Vadd
152
Vcmp, Vcmpe
153
VCVT, VCVTR between Floating-Point and Integer
154
VCVT between Floating-Point and Fixed-Point
155
Vcvtb, Vcvtt
156
VDIV
157
Vfma, Vfms
158
Vfnma, Vfnms
159
Vldm
160
Vldr
161
Vlma, Vlms
162
VMOV Immediate
163
VMOV Register
164
VMOV Scalar to Arm Core Register
165
VMOV Arm Core Register to Single Precision
166
VMOV Two Arm Core Registers to Two Single Precision
167
VMOV Arm Core Register to Scalar
168
Vmrs
169
Vmsr
170
Vmul
171
Vneg
172
Vnmla, Vnmls, Vnmul
173
Vpop
174
Vpush
175
Vsqrt
176
Vstm
177
Vstr
178
Vsub
179
Miscellaneous Instructions
180
Table 36. Miscellaneous Instructions
180
Bkpt
181
Cps
182
Dmb
183
Dsb
184
Isb
185
Mrs
186
Msr
187
Nop
188
Sev
189
Svc
190
Wfe
191
Wfi
192
Core Peripherals
193
About the STM32 Cortex-M4 Core Peripherals
193
Memory Protection Unit (MPU)
193
Table 37. STM32 Core Peripheral Register Regions
193
Table 38. Memory Attributes Summary
194
MPU Access Permission Attributes
195
Table 39. TEX, C, B, and S Encoding
195
Table 40. Cache Policy for Memory Attribute Encoding
195
MPU Mismatch
196
Updating an MPU Region
196
Table 41. AP Encoding
196
Figure 18. Subregion Example
198
MPU Design Hints and Tips
199
Table 42. Memory Region Attributes for STM32
199
MPU Type Register (MPU_TYPER)
200
MPU Control Register (MPU_CTRL)
201
MPU Region Number Register (MPU_RNR)
202
MPU Region Base Address Register (MPU_RBAR)
203
MPU Region Attribute and Size Register (MPU_RASR)
204
Table 43. Example SIZE Field Values
205
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ST STM32F3 Series Application Note (52 pages)
Getting started with touch sensing control on STM32 microcontrollers
Brand:
ST
| Category:
Microcontrollers
| Size: 4 MB
Table of Contents
1 General Information
2
2 Terminology and Principle
3
Terminology
3
Principle
3
Table 1. Change Transfer Principle Documentation
4
Figure 1. Change Transfer Principle
4
3 Document Reference
5
Table 2. References Documentation
5
Figure 2. Main Documentation Tree
5
4 STM32L4 Touch Sensing Controller Online Presentation
6
Figure 3. STM32L4 Online Training
6
Figure 4. STM32L4 Touch Sensing Controller Online Training
6
5 Main Characteristics
7
Description
7
Signal Threshold
7
Figure 5. TSC Characteristics
7
Table 3. Signal Threshold Usage Documentation
8
Figure 6. Stmstudio Outputs
8
Charge Transfer
9
Table 4. Charge Transfer Documentation
9
Figure 7. Incomplete and Complete Charge Transfert Cycle
9
Sensitivity
10
Table 5. Sensitivity Documentation
10
Table 6. Dielectric Constants of Common Materials Used in a Panel Construction
10
Sensor
11
Key
11
Table 7. Key Documentation
11
Figure 8. Sensor Size
11
Linear or Slider
12
Table 8. Linear Touch Sensor Documentation
12
Figure 9. Interlaced Linear Touch Sensor with 3 Channels / 4 Electrodes (Half-Ended Electrodes Design)
12
Rotary or Wheel
13
Table 9. Rotary Sensor Documentation
13
Figure 10. Interlaced Patterned Rotary Sensor with 3 Channels / 3 Electrodes
13
Active Shield or Driven Shield
14
Table 10. Active Shield Documentation
14
Figure 11. Active Shield Principle
14
Layout and PCB
15
Led Rules
15
Table 11. Led Rules Documentation
15
Figure 12. Led Layout Example
15
Figure 13. Example of Cases Where a LED Bypass Capacitor Is Required
15
Electrode Not Located on PCB
16
Table 12. Electrode Documentation
16
Figure 14. Electrode Not Located on PCB Example
16
Ground, Shield and Sensors
17
Table 13. Layout Documentation
17
Figure 15. Hatched Ground and Signal Tracks
17
Figure 16. Ground Plane Example
17
Figure 17. Track Routing
18
Figure 18. Track Routing Recommendation
18
Figure 19. Shield
19
Faq
20
Noise
21
Power Supply
21
False Detection
21
Table 14. Power Supply Documentation
21
Table 15. False Detection Documentation
21
Figure 20. Typical Power Supply Schematic
21
Noise Immunity
22
Conducted Noise
22
Table 16. Noise Immunity Documentation
22
Table 17. Conducted Noise Documentation
22
6 Tuning
23
Table 18. Sensors Documentation
23
Table 19. ESD Documentation
23
Table 20. Conducted Noise Documentation
23
Table 21. Sampling Capacitor Documentation
23
7 Getting Started TSC with Stm32Cubemx
24
Uses Cases
24
Figure 21. Main Project Panel
24
Discovery Board: STM32F072B-DISCO
25
STM32F072B-DISCO Board Selection
25
Figure 22. STM32F072B-DISCO Board Selection
25
Figure 23. STM32F072B-DISCO Board Schematics
25
TSC Group and Sensor Activation
27
Figure 24. STM32F072B-DISCO Pinout SWD
27
Figure 25. STM32F072B-DISCO Pinout TSC
27
STM32F072B-DISCO Clock Tree
28
Figure 26. STM32F072B-DISCO Pinout Overview
28
Figure 27. STM32F072B-DISCO Clock Configuration
28
STM32F072B-DISCO Touchsensing Library
29
Figure 28. TOUCHSENSING Box Configuration
29
Figure 29. STM32F072B-DISCO Sensor Selection
29
Figure 30. STM32F072B-DISCO Sensor Selection Step2
30
Figure 31. STM32F072B-DISCO Sensor Selection Step3
30
Figure 32. STM32F072B-DISCO Sensor Selection Step4
31
Figure 33. STM32F072B-DISCO Sensor Selection Step5
31
STM32F072B-DISCO Software Project Generation
32
Figure 34. STM32F072B-DISCO Software Generation Step1
32
Figure 35. STM32F072B-DISCO Software Generation Step2
32
Figure 36. STM32F072B-DISCO Software Generation Step3
33
Figure 37. STM32F072B-DISCO IDE Workspace
33
Software Basic Algorythm
34
Figure 38. STM32F072B-DISCO Setup
35
Discovery Board: STM32L0538-DISCO
36
STM32L0538-DISCO Board Selection
36
Figure 39. STM32L0538-DISCO Board Selection
36
Figure 40. STM32L0538-DISCO Board Schematics
37
STM32L0538-DISCO TSC Group and Sensor Activation
38
Figure 41. Pinout SWD
38
Figure 42. Pinout TSC
38
STM32L0538-DISCO Clock Tree
39
Figure 43. Pinout Overview
39
Figure 44. Clock Configuration
39
STM32L0538-DISCO Touchsensing Library
40
Figure 45. TOUCHSENSING Box Configuration
40
Figure 46. STM32L0538-DISCO Sensor Selection Step1
40
Figure 47. STM32L0538-DISCO Sensor Selection Step2
41
Figure 48. STM32L0538-DISCO Sensor Selection Step3
41
Figure 49. STM32L0538-DISCO Sensor Selection Step4
42
Figure 50. STM32L0538-DISCO Sensor Selection Step5
42
STM32L0538-DISCO Software Project Generation
43
Figure 51. STM32L0538-DISCO Software Generation Step1
43
Figure 52. STM32L0538-DISCO Software Generation Step2
43
STM32L0538-DISCO Software Basic Algorythm
45
ST STM32F3 Series Application Note (56 pages)
Brand:
ST
| Category:
Microcontrollers
| Size: 3 MB
Table of Contents
General Information
2
Table 2. Glossary
2
Overview
5
Security Purpose
5
Figure 1. Corrupted Connected Device Threat
5
Table 3. Assets to be Protected
6
Attack Types
7
Introduction to Attack Types
7
Software Attacks
8
Table 4. Attacks Types and Costs
8
Hardware Attacks
9
Non-Invasive Attacks
10
Silicon Invasive Attacks
11
Iot System Attack Examples
12
Figure 2. Iot System
12
List of Attack Targets
13
Device Protections
16
Configuration Protection
16
Trustzone ® for Armv8-M Architecture
16
Dual-Core Architecture
17
Figure 3. Armv8-M Trustzone® Execution Modes
17
Figure 4. Simplified Diagram of Dual-Core System Architecture
17
Memory Protections
18
Figure 5. Memory Types
18
System Flash Memory
19
User Flash Memory
19
Embedded SRAM
19
External Flash Memories
20
STM32 Memory Protections
21
Software Isolation
21
Debug Port and Other Interface Protection
21
Boot Protection
22
System Monitoring
22
Secure Applications
23
Secure Firmware Install (SFI)
23
Root and Chain of Trust
23
Stmicroelectronics Proprietary SBSFU Solution
23
Secure Boot (SB)
23
Secure Firmware Update (SFU)
24
Figure 6. Secure Boot FSM
24
Configurations
25
Arm TF-M Solution
25
Figure 7. Secure Server/Device SFU Architecture
25
Product Certifications
26
Table 8. Basic Feature Differences of Trustzone-Based Secure Software
26
STM32 Security Features
27
Overview of Security Features
27
Static and Dynamic Protections
27
Security Features by STM32 Devices
27
Table 10. Security Features for STM32L0/1/4/4+, STM32WB, STM32WL Devices
28
Readout Protection (RDP)
29
Table 11. Security Features for STM32L5, STM32U5, STM32H503/5, Stm32H72X/73/74X/75, Stm32H7Ax/7Bx, STM32F7 Devices
29
Figure 8. Example of RDP Protections (STM32L4 Series)
30
Lifecycle Management-Product State
31
Table 12. RDP Protections
31
One-Time Programmable (OTP)
32
Trustzone
32
Core State
33
Secure Attribution Unit (SAU)
33
Figure 9. Trustzone® Implementation at System Level
33
Memory and Peripheral Protections
34
Flash Memory Write Protection (WRP)
34
Execute-Only Firmware (PCROP)
34
Secure Hide Protection (HDP)
35
Firewall
35
Figure 10. HDP Protected Firmware Access
35
Figure 11. Firewall FSM
36
Figure 12. Firewall Application Example
36
Memory Protection Unit (MPU)
37
Table 13. Attributes and Access Permission Managed by MPU
37
Customer Key Storage (CKS)
38
Table 14. Process Isolation
38
Figure 13. Dual-Core Architecture with CKS Service
38
Antitamper (Tamp)/Backup Registers (BKP)
39
Clock Security System (CSS)
39
Power Monitoring (PVD)
39
Memory Integrity Hardware Check
39
Independent Watchdog (IWDG)
40
Device ID
40
Cryptography
40
Hardware Accelerators
40
Cryptolib Software Library
40
On-The-Fly Decryption Engine (OTFDEC)
41
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