STM32F038x6
Workaround
Increase the I2CCLK frequency to get I2CCLK period within the transmitter minimum data
set-up time. Alternatively, increase transmitter's minimum data set-up time.
2.3.2
Spurious bus error detection in master mode
Description
In master mode, a bus error can be detected by mistake, so the BERR flag can be wrongly
raised in the status register. This will generate a spurious Bus Error interrupt if the interrupt
is enabled. A bus error detection has no effect on the transfer in master mode, therefore the
I2C transfer can continue normally.
Workaround
If a bus error interrupt is generated in master mode, the BERR flag must be cleared by
software. No other action is required and the on-going transfer can be handled normally.
2.3.3
10-bit slave mode: wrong direction bit value after Read header
reception
Description
Under specific conditions, the transfer direction bit DIR (bit 16 of status register I2C_ISR) is
low instead of high after reception of the 10-bit addressing Read header. Nevertheless, the
2
I
C operates correctly in slave transmission mode, and data can be sent using the TXIS
flag.
To see the limitation, all the following conditions have to be fulfilled:
2
•
I
C has to be configured in 10-bit addressing mode (OA1MODE is set in the I2C_OAR1
register).
•
The high LSBs of the I
header value (i.e. OA1[7:3] = 11110, OA1[2] = OA1[9], OA1[1] = OA1[8] and OA1[0] = 1
in the I2C_OAR1 register).
•
The I
start condition to enter slave transmission mode.
As a result, the DIR bit is incorrect in slave mode under specific conditions.
Workaround
If possible, do not use these four values as 10-bit addresses in slave mode:
•
OA1[9:0] = 0011110001
•
OA1[9:0] = 0111110011
•
OA1[9:0] = 1011110101
•
OA1[9:0] = 1111110111
If one of these addresses is the I
2
C slave address are equal to the 10-bit addressing Read
2
C receives the 10-bit addressing Read header (0X 1111 0XX1) after the repeated
DocID026423 Rev 2
2
C slave address, the DIR bit must not be used in the FW.
Description of device limitations
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