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RM0090
CTS
Transmit data register
TDR
TX
Note:
Special behavior of break frames: when the CTS flow is enabled, the transmitter does not
check the CTS input state to send a break.
Universal synchronous asynchronous receiver transmitter (USART)
Figure 319. CTS flow control
Data 2
empty
Stop
Start
Data 1
bit
bit
Writing data 3 in TDR
RM0090 Rev 18
CTS
Data 3
Stop
Data 2
bit
Transmission of Data 3 is
delayed until CTS = 0
CTS
empty
Start
Idle
Data 3
bit
MSv31167V2
1005/1749
1018
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