RM0090
30.5
USART mode configuration
Asynchronous mode
Hardware flow control
Multibuffer communication (DMA)
Multiprocessor communication
Synchronous
Smartcard
Half-duplex (single-wire mode)
IrDA
LIN
1. X = supported; NA = not applicable.
30.6
USART registers
Refer to
used in register descriptions.
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
30.6.1
Status register (USART_SR)
Address offset: 0x00
Reset value: 0x0000 00C0
31
30
29
15
14
13
Reserved
Universal synchronous asynchronous receiver transmitter (USART)
Table 148. USART mode configuration
USART modes
Section 1.1: List of abbreviations for registers
28
27
26
25
12
11
10
9
CTS
rc_w0
USART
USART
1
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
24
23
22
Reserved
8
7
6
LBD
TXE
TC
rc_w0
r
rc_w0
RM0090 Rev 18
(1)
USART
UART4
UART5
3
X
X
X
X
NA
NA
X
X
X
X
X
X
X
NA
NA
X
NA
NA
X
X
X
X
X
X
X
X
X
for registers for a list of abbreviations
21
20
19
18
5
4
3
2
RXNE
IDLE
ORE
NF
rc_w0
r
r
USART
6
X
X
X
X
X
X
X
X
X
17
16
1
0
FE
PE
r
r
r
1007/1749
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