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ADSP-TS201S
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The time for the voltage on the bus to ramp by ΔV is
dependent on the capacitive load, C
This ramp time can be approximated by the following equation:
t
RAMP
The output enable time t
ENA
t
and t
as shown in
MEASURED_ENA
RAMP
t
is the interval from when the reference signal
MEASURED_ENA
switches to when the output voltage ramps ΔV from the mea-
sured three-stated output level. t
, and with ΔV equal to 0.4 V.
C
, drive current I
L
D
Capacitive Loading
Output valid and hold are based on standard capacitive loads:
30 pF on all pins (see
Figure
tions given should be derated by a drive strength related factor
for loads other than the nominal value of 30 pF.
through
Figure 44
show how output rise time varies with capac-
itance.
Figure 45
graphically shows how output valid varies with
load capacitance. (Note that this graph or derating does not
apply to output disable delays; see
Page
37.) The graphs of
Figure 37
linear outside the ranges shown.
TO
OUTPUT
PIN
Figure 36. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
25
20
FALL TIME
15
Y = 0.251x + 4.2245
10
Y = 0.259x + 3.0842
5
0
0
10
20
30
40
LOAD CAPACITANCE (pF)
Figure 37. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 0
, and the drive current, I
L
(
Δ
) I
⁄
C
V
=
L
D
is the difference between
Figure
35. The time
is calculated with test load
RAMP
36). The delay and hold specifica-
Figure 37
Output Disable Time on
through
Figure 45
may not be
50
1.25V
30pF
STRENGTH 0
(V
= 2.5V)
DD_IO
RISE TIME
50
60
70
80
90
100
= 2.5 V)
DD_IO
Rev. C | Page 38 of 48 | December 2006
25
.
20
D
15
10
5
0
0
10
Figure 38. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 1
25
20
15
10
5
0
0
10
Figure 39. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 2
25
20
15
10
5
0
0
10
Figure 40. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 3
STRENGTH 1
(V
= 2.5V)
DD_IO
FALL TIME
Y = 0.1527x + 0.7485
RISE TIME
Y = 0.1501 x + 0.05
20
30
40
50
60
70
80
LOAD CAPACITANCE (pF)
STRENGTH 2
(V
= 2.5V)
DD_IO
FALL TIME
Y = 0.0949x + 0.8112
RISE TIME
Y = 0.0861 x + 0.4712
20
30
40
50
60
70
80
LOAD CAPACITANCE (pF)
STRENGTH 3
(V
= 2.5V)
DD_IO
FALL TIME
Y = 0.0691x + 1.1158
RISE TIME
Y = 0.06 x + 1.1362
20
30
40
50
60
70
80
LOAD CAPACITANCE (pF)
90
100
= 2.5 V)
DD_IO
90
100
= 2.5 V)
DD_IO
90
100
= 2.5 V)
DD_IO
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