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QB-78F1026
4.1.7
P10 to P12, P15, P60 to P63, P111, P121, and P122 pins
The input characteristics of the P10 to P12, P15, P60 to P63, P111, P121, and P122 pins differ between the target
device and emulator.
Target device
IECUBE
Table 4-3. Input Characteristics of P12, P15, P60 to P63, and P111 Pins
Target device
IECUBE
4.1.8
FLMD0 pin
The processing for the FLMD0 pin differs from that of the target device.
Item
Target device
IECUBE
4.1.9
Power-on-clear (POC) voltage value
The power-on-clear (POC) voltage value differs from that of the target device.
Target device
IECUBE
R20UT0290JJ0100 Rev. 1.00
Sep 30, 2010
Table 4-2. Input Characteristics of P10, P11, and P122 Pins
Item
Input Characteristics of P10, P11, and P122 Pins
Schmitt input
CMOS input
Input Characteristics of P12, P15, P60 to P63,
Item
CMOS input
Schmitt input
Table 4-4. FLMD0 Pin Processing
Protection resistance: 4.5 kΩ (TYP.)
Pull-up/pull-down resistors: 10 kΩ (MIN.), 20 kΩ (TYP.), 100 kΩ (MAX.)
Protection resistance: 4.7 kΩ (TYP.)
Pull-up/pull-down resistors: 29 kΩ (MIN.), 30 kΩ (TYP.), 32 kΩ (MAX.)
Table 4-5. Power-on-clear (POC) voltage value
Item
VPOR
1.52 V
VPDR
1.50 V
VPOR
VPDR
and P111 Pins
FLMD0 Pin Processing
MIN.
TYP.
1.61 V
1.59 V
−
1.65 V
−
1.55 V
CHAPTER 4 CAUTIONS
MAX.
1.70 V
1.68 V
−
−
Page 28 of 29
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