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Table 6-3. Limitations on Register Operation
User Interrupt Stack Pointer
UART1 Transmit/Receive Mode Register
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Interrupt Control Register 0
UART Transmit/Receive Control Register 2
UART1 Transmit Buffer Register
UART1 Receive Buffer Register
Port 6 and Port 6 DDR
6.6 Limitations on Interrupts - Vectors that Reside in the Hardware Vector Table
Table 6-4 lists the limitations on hardware interrupt vector addresses.
Table 6-4. Interrupt Vector Addresses
Interrupt Cause
Undefined
Overflow
BRK Instruction
Address Match
Single-step
Watchdog Timer
DBC
NMI
RESET
NOTES:
(1) The Watchdog Timer vector is shared with the oscillation stop and voltage detection
(2) The kernel transparently relocates the Reset vector to FFFD8H.
6.7 Stop or Wait Mode Limitations
The kernel cannot be run in STOP or WAIT modes. Do not use the STOP or WAIT instructions in
your program.
6.8 User Program's Real-Time Capability
Please be aware that while the kernel is in a "STOP" state, the hardware peripherals will continue
to run. Therefore, interrupts may not be serviced properly. Also, the watchdog timer will not be
serviced and will likely time out if active.
While the kernel is in a "RUN" state, there is no overhead on the application code, UNLESS a
RAM monitor window is open in KD30. This window requires periodic communication with the
MCU. This communication suspends normal application operation while servicing the request
(approximately 2000 BCLK cycles for each 16 bytes of data displayed in the window are used per
window update). The user must determine whether or not this behavior is acceptable.
SKP16C62P User's Manual Rev. 1.0
Downloaded from
Elcodis.com
electronic components distributor
Register Name
M16C/62P Vector
Address
FFFDCH ~ FFFDFH
FFFE0H ~ FFFE3H
FFFE4H ~ FFFE7H
FFFE8H ~ FFFEBH
FFFECH ~ FFFEFH
FFFF0H ~ FFFF3H
FFFF4H ~ FFFF7H
FFFF8H ~ FFFFBH
FFFFCH ~ FFFFFH
interrupt. The vector is available for oscillation stop and voltage detection interrupts, but
not Watchdog Timer interrupts.
Restriction
Range 7B80H – 7BFFH is used by the kernel
Do not change
Do not change
Do not change bits 0 and 2
Do not write to this register
Do not read this register
To prevent changes on P6_4 data and direction,
use read-modify-write only instructions (BSET,
BCLR, AND, OR, etc)
Kit Specification
User available
User available
User inhibited
User inhibited
User inhibited
User available (Note 1)
User inhibited
User available
Reset vector (Note 2)
12 / 22
Applications Engineering
December 2003
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