Otg_Hs Global Registers; Table 164. Data Fifo (Dfifo) Access Register Map; Table 165. Power And Clock Gating Control And Status Registers - ST STM32F205 series Reference Manual

RM0033
Table 163. Device-mode control and status registers (continued)
Acronym
OTG_HS_DOEPINTx
OTG_HS_DOEPTSIZx
Data FIFO (DFIFO) access register map
These registers, available in both host and peripheral modes, are used to read or write the
FIFO space for a specific endpoint or a channel, in a given direction. If a host channel is of
type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type
OUT, the FIFO can only be written on the channel.
Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access
Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access
Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access
Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access
...
Device IN Endpoint x
Device OUT Endpoint x
1. Where x is 5 in peripheral mode and 11 in host mode.
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and
peripheral modes.
Power and clock gating control register
Reserved
30.12.2

OTG_HS global registers

These registers are available in both host and peripheral modes, and do not need to be
reprogrammed when switching between these modes.
Offset
address
0xB08
OTG_HS device endpoint-x interrupt register
0xB28
(OTG_HS_DOEPINTx) (x = 0..7, where x = Endpoint_number) on
...
page 1182
0xBC8
0xB30
OTG_HS device endpoint-x transfer size register
0xB50
(OTG_HS_DOEPTSIZx) (x = 1..5, where x = Endpoint_number)
...
on page 1186
0xBD0

Table 164. Data FIFO (DFIFO) access register map

FIFO access register section
(1)
/Host OUT Channel x
(1)
/Host IN Channel x

Table 165. Power and clock gating control and status registers

Register name
RM0033 Rev 8
USB on-the-go high-speed (OTG_HS)
Register name
(1)
: DFIFO Write Access
(1)
: DFIFO Read Access
Acronym
OTG_HS_PCGCCTL
-
Address range
0x1000–0x1FFC
0x2000–0x2FFC
...
0xX000–0xXFFC
Offset address: 0xE00–0xFFF
0xE00-0xE04
0xE05–0xFFF
1123/1378
Access
w
r
w
r
...
w
r
1258