Parity Error Signal Output - Renesas M16C/29 Series Hardware Manual

M16C/29 Group
Figure 14.1.6.2 shows the example of connecting the SIM interface. Connect T
pull-up.
Figure 14.1.6.2. SIM Interface Connection

14.1.6.1 Parity Error Signal Output

The parity error signal is enabled by setting the U2C1 register's U2ERE bit to "1".
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TxD2 output low with the timing shown in Figure 14.1.6.1.1. If the R2RB register is read
while outputting a parity error signal, the PER bit is cleared to "0" and at the same time the TxD2 output
is returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse
that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service
routine.
Transfer
clock
RxD
TxD
U2C1 register
RI bit
This timing diagram applies to the case where the direct format is
implemented.
Note: The output of microcomputer is in the high-impedance state
(pulled up externally).
Figure 14.1.6.1.1. Parity Error Signal Output Timing
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Microcomputer
TxD
2
RxD
2
"H"
"L"
"H"
ST D0
2
"L"
"H"
2
"L"
"1"
"0"
page 207 of 402
14.1.6 Special Mode 4 (SIM Mode) (UART2)
SIM card
D1 D2 D3 D4 D5
(Note)
D and R D
X 2 X
D6 D7 P SP
ST : Start bit
P : Even Parity
SP : Stop bit
and apply
2