Renesas M16C/29 Series Hardware Manual page 427

REVISION HISTORY
Rev. Date
Page
80, 81
118
121
133 to 138 Figure 13.1 to 13.6 are partly revised.
141
150
161
198
209
210
214
253,254 Figure 16.6 and Figure 16.7 are partly revised.
261
266
275
296
306
337
368
367,368 "21.2 Memory Map" is partly revised.
372
373
374
375
383
390
391,392 Figure 21.9.1 and Figure 21.9.2 are partly revised.
393,394 Figure 21.9.2.1 and Figure 21.9.2.2 are partly revised.
396
397,398 Figure 21.11.1 and Figure 21.11.2 are partly revised.
399
66 "9.3 Interrupt Control" is partly revised.
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76 "9.6 INT Interrupt" and "9.7 NMI Interrupt" are partly revised.
77 "9.8 Key Input Interrupt" and "9.9 CAN0 Wake-up Interrupt" are partly revised.
80 "10. Watchdog Timer" is partly revised.
"10.1 Count source protective mode" is partly revised.
81 Note 2 in Figure 10.2 is revised.
Figure 12.3.1 is partly revised.
"Three-phase output buffer register" in Figure 12.3.4 is partly revised.
"Function enable register" in Figure 13.9 is partly revised.
Table 13.4.1 is partly revised.
"13.6 I/O Port Function Select" is partly revised.
Figure 14.1.4.1 is partly revised.
Figure 14.2.1 is partly revised.
Figure 14.2.2 is partly revised.
"Integral Nonlinearity Error" in Table 15.1 is partly revised.
"16.5.4 Bit 3: Arbitration lost detection flag" is partly revised.
"16.6.5 I2C system clock select bits" and Talbe 16.6 are partly revised.
"9)" in "16.13.2 Example of Slave Receive" is revised.
"17.3 Configuration of the CAN Module System Clock" is partly revised.
"18.1 CRC snoop" is partly revised.
Table 20.25 is partly revised.
"21.1 Flash Memory Performance" is partly revised.
"21.4 CPU Rewrite Mode" is partly revised.
"21.4.1 EW0 Mode" and "21.4.2 EW1 Mode" are partly revised.
"FMR01 Bit" is partly revised.
"FMR17 Bit" is partly revised.
"21.7.4 Program Command (40
Table 21.9.1 and Note 2 are partly revised.
Table 21.11.1 and Note 1 are partly revised.
Figure 21.11.3 is partly revised.
M16C/29 Hardware Manual
Description
Summary
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)" is partly revised.
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