Renesas M16C/29 Series Hardware Manual page 189

M16C/29 Group
UARTi transmit/receive control register 0 (i=0 to 2)
b7 b6 b5 b4 b3 b2
Note 1: Set the corresponding port direction bit for each CTSi pin to "0" (input mode).
Note 2: Effective for clock synchronous serial I/O mode, UART mode transfer data 8 bits long and special mode 2.
Note 3: CTS /RTS
1 1
"0" (CTS /RTS
0
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register's CKDIR bit = "0" (internal clock)
Figure 14.1.6. Serial I/O-related registers (3)
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
b1 b0
Symbol
U0C0 to U2C0 03A4
Bit
Bit name
symbol
CLK0 BRG count source
select bit
CLK1
CRS CTS/RTS function
select bit
(Note 3)
TXEPT Transmit register empty
flag
CRD CTS/RTS disable bit
Data output select bit
NCH
CKPOL CLK polarity select bit
UFORM Transfer format select bit
(Note 2)
can be used when the UCON register's CLKMD1 bit = "0" (only CLK
not separated).
0
b1 b0
Symbol
UCON
Bit
Bit
symbol
name
U0IRS UART0 transmit
interrupt cause select bit
U1IRS UART1 transmit
interrupt cause select bit
U0RRM UART0 continuous
receive mode enable bit
U1RRM UART1 continuous
receive mode enable bit
CLKMD0 UART1 CLK/CLKS
select bit 0
CLKMD1 UART1 CLK/CLKS
select bit 1 (Note)
RCSP Separate UART0
CTS/RTS bit
Nothing is assigned. When write, set "0". When read, its content is indeterminate.
(b7)
page 169 of 402
Address After reset
, 03AC , 037C 00001000
16 16 16 2
b1 b0
0 0 : f or f is selected
1SIO 2SIO
0 1 : f is selected
8SIO
1 0 : f is selected
32SIO
1 1 : Must not be set
Effective when CRD = 0
0 : CTS function is selected (Note 1)
1 : RTS function is selected
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6 , P6 and P7 can be used as I/O ports)
0 4 3
0 : TxDi/SDAi and SCLi pins are CMOS output
1 : TxDi/SDAi and SCLi pins are N-channel open-drain output
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
0 : LSB first
1 : MSB first
Address After reset
03B0 X0000000
16 2
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enable
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Effective when CLKMD1 = "1"
0 : Clock output from CLK1
1 : Clock output from CLKS1
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins function
selected
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS
14.1 UARTi (i=0 to 2)
Function
output) and the UCON register's RCSP bit =
1
Function
supplied from the P6
0
RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
pin)
4