Special Mode 1 (I 2 C Bus Mode)(Uart2) - Renesas M16C/29 Series Hardware Manual

M16C/29 Group
14.1.3 Special Mode 1 (I
2
I C bus mode is provided for use as a simplified I
the specifications of the I
mode and the register values set. Table 14.1.3.4 lists the I
the block diagram for I
As shown in Table 14.1.3.2, the microcomputer is placed in I
bits to '010 ' and the IICM bit to "1". Because SDA
2
output does not change state until SCL
2
Table 14.1.3.1. I C bus Mode Specifications
Item
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Select function
Note 1: When an external clock is selected, the conditions must be met while the external clock is in the
high state.
Note 2: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC
register does not change.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
2
C bus mode)(UART2)
2
C bus mode. Table 14.1.3.2 and 14.1.3.3 list the registers used in the I
2
C bus mode. Figure 14.1.3.2 shows SCL
2
• Transfer data length: 8 bits
• During master
U2MR register's CKDIR bit = "0" (internal clock) : fj/ 2(n+1)
fj = f , f
1SIO 2SIO
• During slave
CKDIR bit = "1" (external clock) : Input from SCL pin
• Before transmission can start, the following requirements must be met (Note 1)
_
The TE bit of U2C1 register= 1 (transmission enabled)
_
The TI bit of U2C1 register = 0 (data present in U2TB register)
• Before reception can start, the following requirements must be met (Note 1)
_
The RE bit of U2C1 register= 1 (reception enabled)
_
The TE bit of U2C1 register= 1 (transmission enabled)
_
The TI bit of U2C1 register= 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 8th bit of the next data
• Arbitration lost
Timing at which the U2RB register's ABT bit is updated can be selected
• SDA digital delay
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
page 187 of 402
14.1.3 Special Mode 1 (I
2
C bus interface compatible mode. Table 14.1.3.1 lists
2
C bus mode fuctions. Figure 14.1.3.1 shows
2
C bus mode by setting the SMD2 to SMD0
transmit output has a delay circuit attached, SDA
2
goes low and remains stably low.
Specification
, f , f . n: Setting value of U2BRG register
8SIO 32SIO
2
C bus mode) (UART2)
timing.
2
2
C bus
00 to FF
16 16