Renesas M16C/29 Series Hardware Manual page 88

M16C/29 Group
Interrupt request cause select register
b7 b6 b5 b4 b3
Note 1: When setting this bit to "1" (= both edges), make sure the INT0IC to INT5IC register's POL bit
is set to "0" (= falling edge).
Note 2: When setting this bit to "0" (= SI/O3, SI/O4), make sure the S3IC and S4IC registers' POL bit is
set to "0" (= falling edge).
Interrupt request cause select register 2
b7 b6 b5 b4 b3
Figure 9.3.2. IFSR Register and IFSR2A Register
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
b2 b1 b0
Symbol
IFSR
Bit symbol
IFSR0 INT0 interrupt polarity
switching bit
IFSR1 INT1 interrupt polarity
switching bit
IFSR2 INT2 interrupt polarity
switching bit
IFSR3 INT3 interrupt polarity
switching bit
IFSR4 INT4 interrupt polarity
switching bit
IFSR5 INT5 interrupt polarity
switching bit
IFSR6 Interrupt request cause
select bit
IFSR7 Interrupt request cause
select bit
b2 b1 b0
0 Symbol
IFSR2A
Bit symbol
Reserved bit
IFSR20
Interrupt request cause
IFSR21
select bit
Interrupt request cause
IFSR22
select bit
Nothing is assigned. When write, set to "0".
(b5-b3)
When read, their contents are indeterminate.
Interrupt request cause
IFSR26
select bit
Interrupt request cause
IFSR27
select bit
page 68 of 402
Address After reset
035F 00
16
16
Bit name
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : SI/O3
1 : INT4
0 : SI/O4
1 : INT5
Address After reset
035E 00XXX000
16
Bit name
Must be set to "0".
0 : A/D conversion
1 : Key input
0 : CAN0 wakeup/error
1 : Must not be set
0 : ICOC base timer
1 : S /S
CL
0 : ICOC interrupt 1
2
1 : I C bus interface
Function
RW
RW
(Note 1)
RW
(Note 1)
RW
(Note 1)
RW
(Note 1)
RW
(Note 1)
RW
(Note 1)
(Note 2)
RW
(Note 2)
RW
2
Function
RW
RW
RW
RW
RW
DA
RW
9. Interrupts