I Flag; Ir Bit; Ilvl2 To Ilvl0 Bits And Ipl - Renesas M16C/29 Series Hardware Manual

M16C/29 Group

9.3.1 I Flag

The I flag enables or disables the maskable interrupt. Setting the I flag to "1" (= enabled) enables the
maskable interrupt. Setting the I flag to "0" (= disabled) disables all maskable interrupts.

9.3.2 IR Bit

The IR bit is set to "1" (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to "0" (= interrupt not requested).
The IR bit can be cleared to "0" in a program. Note that do not write "1" to this bit.

9.3.3 ILVL2 to ILVL0 Bits and IPL

Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt priority
levels enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = "1"
· IR bit = "1"
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect
one another.
Table 9.3.3.1. Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 bits
Level 0 (interrupt disabled)
000
2
Level 1
001
2
010 Level 2
2
011 Level 3
2
100 Level 4
2
101 Level 5
2
110 Level 6
2
111 Level 7
2
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Interrupt priority Priority
level order
page 69 of 402
Table 9.3.3.2. Interrupt Priority Levels
IPL
000
001
Low
010
011
100
101
110
111
High
Enabled by IPL
Enabled interrupt priority levels
Interrupt levels 1 and above are enabled
2
Interrupt levels 2 and above are enabled
2
2 Interrupt levels 3 and above are enabled
2 Interrupt levels 4 and above are enabled
2 Interrupt levels 5 and above are enabled
2 Interrupt levels 6 and above are enabled
2 Interrupt levels 7 and above are enabled
2 All maskable interrupts are disabled
9. Interrupts